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arghunterarghunter
committed
added buttons
1 parent d0020ca commit 0aa3ad6

29 files changed

Lines changed: 334 additions & 9 deletions

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/constrs_1/new/master.xdc‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,10 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk
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## Reset (btnC)
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set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports btnC]
7-
7+
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports btnU]
8+
set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports btnL]
9+
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports btnR]
10+
set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports btnD]
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## UART
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set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports RsRx]
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set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports RsTx]

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.srcs/sources_1/new/top.v‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,10 @@
22
module Top(
33
input wire clk,
44
input wire btnC,
5+
input wire btnR,
6+
input wire btnU,
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input wire btnD,
8+
input wire btnL,
59
input wire RsRx,
610
output wire RsTx,
711
output wire [15:0] led,
@@ -20,7 +24,7 @@ module Top(
2024
else clk_div <= clk_div + 2'h1;
2125
end
2226
wire clk_25 = clk_div[1];
23-
27+
wire [3:0] btns = {btnU,btnR,btnL,btnD};
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// -------------------------------------------------------
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// UART program loader
2630
// -------------------------------------------------------
@@ -61,7 +65,9 @@ module Top(
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.io_hsync (vgaHSync),
6266
.io_vsync (vgaVSync),
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.io_rgb (rgb),
64-
.io_blanking (blanking)
68+
.io_blanking (blanking),
69+
.btns(btns)
70+
6571
);
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6773
assign vgaRed = blanking ? 4'h0 : rgb[11:8];

‎RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr‎

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
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7-
<Project Product="Vivado" Version="7" Minor="71" Path="C:/Users/outer/OneDrive/Desktop/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
7+
<Project Product="Vivado" Version="7" Minor="71" Path="/home/arya/Documents/Github/RISC-V/RISC-V-Scaffold-Basys3/RISC-V-Scaffold-Basys3.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="5ccae5db352846dd96f73584352a58b3"/>
@@ -90,15 +90,15 @@
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<FileSets Version="1" Minor="32">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
9292
<Filter Type="Srcs"/>
93-
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
93+
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
9494
<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
100100
</File>
101-
<File Path="$PSRCDIR/sources_1/new/VGATop.v">
101+
<File Path="$PPRDIR/../generated/memory_1024x32_0.sv">
102102
<FileInfo>
103103
<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
@@ -260,12 +260,15 @@
260260
<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
262262
</Simulator>
263+
<Simulator Name="Xcelium">
264+
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
265+
</Simulator>
266+
<Simulator Name="VCS">
267+
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
268+
</Simulator>
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<Simulator Name="Riviera">
264270
<Option Name="Description" Val="Riviera-PRO Simulator"/>
265271
</Simulator>
266-
<Simulator Name="ActiveHDL">
267-
<Option Name="Description" Val="Active-HDL Simulator"/>
268-
</Simulator>
269272
</Simulators>
270273
<Runs Version="1" Minor="22">
271274
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/Top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">

‎RISC-V-Scaffold-Basys3/program.hex‎

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1+
00108093
2+
FE1FF06F

‎RISC-V-Scaffold-Basys3/program10.hex‎

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00004137
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00408093
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00112023
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FF9FF06F

‎RISC-V-Scaffold-Basys3/program11.hex‎

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00108093
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FFDFF06F

‎RISC-V-Scaffold-Basys3/program12.hex‎

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00004137
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00408093
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00112023
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FF9FF06F

‎RISC-V-Scaffold-Basys3/program13.hex‎

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00004137
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FFF0E093
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00112023
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FF9FF06F

‎RISC-V-Scaffold-Basys3/program14.hex‎

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00004137
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FFF00093
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00112023
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FF9FF06F

‎RISC-V-Scaffold-Basys3/program15.hex‎

Lines changed: 2 additions & 0 deletions
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00108093
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FF9FF06F

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