Add writing full instruction for debug

Author: outercloudstudio

src/main/scala/main/Core.scala

@@ -8,7 +8,9 @@ class Core extends Module {
 
     val debug_memory_write = Input(Bool());
     val debug_memory_write_address = Input(UInt(8.W));
-    val debug_memory_write_data = Input(UInt(8.W));
+    val debug_memory_write_data_0 = Input(UInt(8.W));
+    val debug_memory_write_data_1 = Input(UInt(8.W));
+    val debug_memory_write_data_2 = Input(UInt(8.W));
 
     val debug_dispatcher_opcode = Output(Operation());
     val debug_dispatcher_program_pointer = Output(UInt(8.W));
@@ -23,17 +25,27 @@ class Core extends Module {
   memory.io.readPorts(0).enable := dispatcher.io.read_requested;
   memory.io.readPorts(0).address := 3.U * dispatcher.io.read_program_pointer;
   memory.io.readPorts(1).enable := dispatcher.io.read_requested;
-  memory.io.readPorts(1).address := 3.U * dispatcher.io.read_program_pointer + 1.U;
+  memory.io
+    .readPorts(1)
+    .address := 3.U * dispatcher.io.read_program_pointer + 1.U;
   memory.io.readPorts(2).enable := dispatcher.io.read_requested;
-  memory.io.readPorts(2).address := 3.U * dispatcher.io.read_program_pointer + 2.U;
+  memory.io
+    .readPorts(2)
+    .address := 3.U * dispatcher.io.read_program_pointer + 2.U;
 
   memory.io.writePorts(0).enable := io.debug_memory_write;
-  memory.io.writePorts(0).address := io.debug_memory_write_address;
-  memory.io.writePorts(0).data := io.debug_memory_write_data;
+  memory.io.writePorts(0).address := io.debug_memory_write_address * 3.U;
+  memory.io.writePorts(0).data := io.debug_memory_write_data_0;
+  memory.io.writePorts(1).enable := io.debug_memory_write;
+  memory.io.writePorts(1).address := io.debug_memory_write_address * 3.U + 1.U;
+  memory.io.writePorts(1).data := io.debug_memory_write_data_1;
+  memory.io.writePorts(2).enable := io.debug_memory_write;
+  memory.io.writePorts(2).address := io.debug_memory_write_address * 3.U + 2.U;
+  memory.io.writePorts(2).data := io.debug_memory_write_data_2;
 
   dispatcher.io.thread_requesting_opcode := thread.io.idle && io.execute;
   dispatcher.io.thread_program_pointer := thread.io.program_pointer;
-  
+
   val read_ready_delayed = RegNext(dispatcher.io.read_requested, false.B);
   dispatcher.io.read_ready := read_ready_delayed;
   dispatcher.io.read_opcode := memory.io.readPorts(0).data(7, 0);
@@ -42,13 +54,19 @@ class Core extends Module {
 
   when(true.B) {
     printf(p"\t[Core]=====");
-    printf(p"\n\t\tdispatcher.io.read_requested=${dispatcher.io.read_requested}");
-    printf(p"\n\t\tdispatcher.io.read_program_pointer=${dispatcher.io.read_program_pointer}");
+    printf(
+      p"\n\t\tdispatcher.io.read_requested=${dispatcher.io.read_requested}"
+    );
+    printf(
+      p"\n\t\tdispatcher.io.read_program_pointer=${dispatcher.io.read_program_pointer}"
+    );
     printf(p"\n\t\tdispatcher.io.read_opcode=${dispatcher.io.read_opcode}");
     // printf(p"\n\t\tread_ready_delayed=${read_ready_delayed}");
     printf(p"\n\t\tdispatcher_read_ready=${dispatcher.io.read_ready}");
     printf(p"\n\t\tdebug_dispatcher_opcode=${io.debug_dispatcher_opcode}");
-    printf(p"\n\t\tdebug_dispatcher_program_pointer=${io.debug_dispatcher_program_pointer}");
+    printf(
+      p"\n\t\tdebug_dispatcher_program_pointer=${io.debug_dispatcher_program_pointer}"
+    );
     printf(p"\n\t\texecute=${io.execute}");
     printf(p"\n\n");
   }
@@ -61,7 +79,10 @@ class Core extends Module {
   thread.io.operation := dispatcher.io.opcode;
   thread.io.src_register := dispatcher.io.src_register;
   thread.io.dst_register := dispatcher.io.dst_register;
-  thread.io.immediate := Cat(dispatcher.io.read_immediate_u, dispatcher.io.read_immediate_l);
+  thread.io.immediate := Cat(
+    dispatcher.io.read_immediate_u,
+    dispatcher.io.read_immediate_l
+  );
 
   io.debug_thread_debug_output := thread.io.debug_output;
 }

src/main/scala/main/Memory.scala

@@ -3,13 +3,15 @@ import chisel3.util._
 import _root_.circt.stage.ChiselStage
 
 class Memory extends Module {
-  val io = IO(new SRAMInterface(1024, UInt(8.W), 3, 1, 0));
+  val io = IO(new SRAMInterface(1024, UInt(8.W), 3, 3, 0));
 
-  val memory = SRAM(1024, UInt(8.W), 3, 1, 0);
+  val memory = SRAM(1024, UInt(8.W), 3, 3, 0);
 
   io.readPorts(0) <> memory.readPorts(0);
   io.readPorts(1) <> memory.readPorts(1);
   io.readPorts(2) <> memory.readPorts(2);
-  
+
   io.writePorts(0) <> memory.writePorts(0);
+  io.writePorts(1) <> memory.writePorts(1);
+  io.writePorts(2) <> memory.writePorts(2);
 }

src/test/scala/main/CoreTest.scala

@@ -7,63 +7,27 @@ class CoreTest extends AnyFlatSpec with ChiselScalatestTester {
     test(new Core) { dut =>
       dut.io.debug_memory_write.poke(true.B);
       dut.io.debug_memory_write_address.poke(0.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00001010.U(8.W));
-      
-      println("[CoreTest]=====");
-      dut.clock.step(1);
-
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(1.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b01000000.U(8.W));
-    
-      println("[CoreTest]=====");
-      dut.clock.step(1);
-
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(2.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
-
-      println("[CoreTest]=====");
-      dut.clock.step(1);
-
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(3.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00001000.U(8.W));
-      
-      println("[CoreTest]=====");
-      dut.clock.step(1);
-
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(4.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00100010.U(8.W));
-    
-      println("[CoreTest]=====");
-      dut.clock.step(1);
-
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(5.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
+      dut.io.debug_memory_write_data_0.poke(0b00001010.U(8.W));
+      dut.io.debug_memory_write_data_1.poke(0b01000000.U(8.W));
+      dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);
 
       dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(6.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00100000.U(8.W));
-      
-      println("[CoreTest]=====");
-      dut.clock.step(1);
+      dut.io.debug_memory_write_address.poke(1.U(8.W));
+      dut.io.debug_memory_write_data_0.poke(0b00001000.U(8.W));
+      dut.io.debug_memory_write_data_1.poke(0b00100010.U(8.W));
+      dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
 
-      dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(7.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
-    
       println("[CoreTest]=====");
       dut.clock.step(1);
 
       dut.io.debug_memory_write.poke(true.B);
-      dut.io.debug_memory_write_address.poke(8.U(8.W));
-      dut.io.debug_memory_write_data.poke(0b00000000.U(8.W));
+      dut.io.debug_memory_write_address.poke(2.U(8.W));
+      dut.io.debug_memory_write_data_0.poke(0b00100000.U(8.W));
+      dut.io.debug_memory_write_data_1.poke(0b00000000.U(8.W));
+      dut.io.debug_memory_write_data_2.poke(0b00000000.U(8.W));
 
       println("[CoreTest]=====");
       dut.clock.step(1);