Reduce delay in parsing read instructions by one clock cycle

Author: outercloudstudio

src/main/scala/main/Core.scala

@@ -43,7 +43,6 @@ class Core extends Module {
   when(true.B) {
     printf(p"\t[Core]=====");
     printf(p"\n\t\tdispatcher.io.read_requested=${dispatcher.io.read_requested}");
-    printf(p"\n\t\tread_ready_delayed=${read_ready_delayed}");
     printf(p"\n\t\tdispatcher.io.read_program_pointer=${dispatcher.io.read_program_pointer}");
     printf(p"\n\t\tdispatcher.io.read_opcode=${dispatcher.io.read_opcode}");
     // printf(p"\n\t\tread_ready_delayed=${read_ready_delayed}");

src/main/scala/main/Dispatcher.scala

@@ -2,7 +2,6 @@ import chisel3._
 import chisel3.util._
 import _root_.circt.stage.ChiselStage
 
-// TODO: Make dispatcher instantly drive value
 class Dispatcher extends Module {
   val io = IO(new Bundle {
     val thread_requesting_opcode = Input(Bool());
@@ -21,7 +20,7 @@ class Dispatcher extends Module {
     val dst_register = Output(Register());
     val program_pointer = Output(UInt(8.W));
   });
-  
+
   io.read_program_pointer := io.thread_program_pointer;
   io.read_requested := false.B;
 
@@ -49,43 +48,65 @@ class Dispatcher extends Module {
     printf(p"\n\t\tImmediate Lower ${io.read_immediate_l}");
     printf(p"\n\t\tImmediate Upper ${io.read_immediate_u}\n\n");
 
-    opcode := Operation.safe(io.read_opcode(6, 3))._1;
+    val read_opcode = Operation.safe(io.read_opcode(6, 3))._1;
+    opcode := read_opcode;
+    io.opcode := read_opcode;
 
     val registers_code = io.read_opcode(2, 0);
 
     when(registers_code === 0.U) {
       src_register := Register.A;
       dst_register := Register.B;
+
+      io.src_register := Register.A;
+      io.dst_register := Register.B;
     }
 
     when(registers_code === 1.U) {
       src_register := Register.A;
       dst_register := Register.C;
+
+      io.src_register := Register.A;
+      io.dst_register := Register.C;
     }
 
     when(registers_code === 2.U) {
       src_register := Register.B;
       dst_register := Register.A;
+
+      io.src_register := Register.B;
+      io.dst_register := Register.A;
     }
 
     when(registers_code === 3.U) {
       src_register := Register.B;
       dst_register := Register.C;
+
+      io.src_register := Register.B;
+      io.dst_register := Register.C;
     }
 
     when(registers_code === 4.U) {
       src_register := Register.C;
       dst_register := Register.A;
+
+      io.src_register := Register.C;
+      io.dst_register := Register.A;
     }
 
     when(registers_code === 5.U) {
       src_register := Register.C;
       dst_register := Register.B;
+
+      io.src_register := Register.C;
+      io.dst_register := Register.B;
     }
 
     opcode_loaded := true.B;
+    io.opcode_loaded := true.B;
 
     program_pointer := io.read_program_pointer;
+    io.program_pointer := io.read_program_pointer;
 
     io.read_requested := false.B;
   }

src/main/scala/main/Thread.scala

@@ -99,6 +99,11 @@ class Thread extends Module {
       when(io.dst_register === Register.C) {
         register_c := io.immediate
       }
+
+      program_counter.io.update := true.B;
+      program_counter.io.branch := false.B;
+
+      io.idle := false.B;
     }
 
     when(io.operation === Operation.MoveRegister) {