| Name | Definition |
|---|---|
| CommonHeader | Platform Management FRU Information Storage Definition, Table 8-1 |
| ChassisInfo | Platform Management FRU Information Storage Definition, Table 10-1 |
| BoardInfo | Platform Management FRU Information Storage Definition, Table 11-1 |
| ProductInfo | Platform Management FRU Information Storage Definition, Table 12-1 |
| InternalUse | Platform Management FRU Information Storage Definition, Table 9-1 |
| MultirecordArea | Platform Management FRU Information Storage Definition, Table 16-1 |
| Name | Definition |
|---|---|
| PowerSupplyInformation | Platform Management FRU Information Storage Definition, Table 18-1 |
| DCOutput | Platform Management FRU Information Storage Definition, Table 18-2 |
| DCLoad | Platform Management FRU Information Storage Definition, Table 18-4 |
| MgmtAccessRecord | Platform Management FRU Information Storage Definition, Table 18-6 |
| PicmgEntry | PICMG AMC.0 Specification R2.0 |
| FmcEntry | ANSI/VITA 57.1 FMC Standard |
| OemXilinxEntry | Xilinx proprietary, not published |
| OemXilinxD3Entry | Xilinx proprietary, not published |
| Name | Definition |
|---|---|
| ModuleCurrentRequirements | PICMG AMC.0 Specification R2.0, Table 3-10 |
| PointToPointConnectivity | PICMG AMC.0 Specification R2.0, Table 3-16 |
| ClockConfig | PICMG AMC.0 Specification R2.0, Table 3-35 |
| Zone3InterfaceCompatibility | PICMG MicroTCA.4 Enhancements for Rear I/O and Timing R1.0, Table 3-3 |
| FruPartition | PICMG Specification MTCA.0 R1.0, Table 3-10 |
| CarrierManagerIPLink | PICMG Specification MTCA.0 R1.0, Table 3-12 |
| MtcaCarrierInformation | PICMG Specification MTCA.0 R1.0, Table 3-16 |
| PowerPolicyRecord | PICMG Specification MTCA.0 R1.0, Table 3-23 |
| MtcaCarrierActivationPm | PICMG Specification MTCA.0 R1.0, Table 3-25 |
| CarrierP2pConnectivity | PICMG AMC.0 Specification R2.0, Table 3-13 |
| CarrierClkP2pConnectivity | PICMG AMC.0 Specification R2.0, Table 3-29 |
| CarrierBusedConnectivity | PICMG MicroTCA.4 Enhancements for Rear I/O and Timing R1.0, Table 3-12 |
| Zone3InterfaceDocumentation | PICMG MicroTCA.4 Enhancements for Rear I/O and Timing R1.0, Table 3-15 |
| Name | Definition |
|---|---|
| AmcChannelDescriptor | PICMG AMC.0 Specification R2.0, Table 3-17 |
| AmcLinkDescriptor | PICMG AMC.0 Specification R2.0, Table 3-19 |
| DirectClockDescriptor | PICMG AMC.0 Specification R2.0, Table 3-38 |
| IndirectClockDescriptor | PICMG AMC.0 Specification R2.0, Table 3-37 |
| ClockConfigDescriptor | PICMG AMC.0 Specification R2.0, Table 3-36 |
| PartitionDescriptor | PICMG Specification MTCA.0 R1.0, Table 3-11 |
| SlotEntry | PICMG Specification MTCA.0 R1.0, Table 3-17 |
| PowerPolicyDescriptor | PICMG Specification MTCA.0 R1.0, Table 3-24 |
| MtcaCarrierActivCurrDescriptor | PICMG Specification MTCA.0 R1.0, Table 3-26 |
| P2pPortDescriptor | PICMG AMC.0 Specification R2.0, Table 3-15 |
| P2pAmcResourceDescriptor | PICMG AMC.0 Specification R2.0, Table 3-14 |
| P2pClockConnectionDescriptor | PICMG AMC.0 Specification R2.0, Table 3-32 |
| ClockP2pResourceDescriptor | PICMG AMC.0 Specification R2.0, Table 3-30 |
| BusedDeviceDescriptor | PICMG MicroTCA.4 Enhancements for Rear I/O and Timing R1.0, Table 3-14 |
| BusedConnectionDescriptor | PICMG MicroTCA.4 Enhancements for Rear I/O and Timing R1.0, Table 3-13 |
| Name | Definition |
|---|---|
| FmcMainDefinition | ANSI/VITA 57.1 FMC Standard, Table 7 |
| FmcPlusMainDefinition | ANSI/VITA 57.4-2018 FMC+ Standard, Table 5.3.1-1 |
| FmcI2cDeviceDefinition | ANSI/VITA 57.1 FMC Standard, Table 9 |
| Name | Definition |
|---|---|
| DutXilinxMac | None |
| SysCtrlXilinxMac | None |
| XilinxOemD3 | None |