Skip to content

Commit 58af041

Browse files
authored
Merge pull request #10035 from AcKoucher/rcx-fix-short-marking
rcx: ensure that short junctions are always identified and marked
2 parents ed5a5bc + 8a68a9d commit 58af041

6 files changed

Lines changed: 26897 additions & 1 deletion

File tree

src/rcx/src/netRC.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -833,7 +833,7 @@ uint32_t extMain::makeNetRCsegs(dbNet* net, bool skipStartWarning)
833833
uint32_t srcJid;
834834
dbWire* wire = net->getWire();
835835
dbWirePathItr pitr;
836-
if (_mergeResBound != 0.0 || _mergeViaRes) {
836+
{
837837
dbWirePath path;
838838
for (pitr.begin(wire); pitr.getNextPath(path);) {
839839
if (!path.bterm && !path.iterm && path.is_branch && path.junction_id) {

src/rcx/test/BUILD

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ COMPULSORY_TESTS = [
1919
"names",
2020
"net_name_consistency",
2121
"coordinates",
22+
"no_merging",
2223
]
2324

2425
# From CMakeLists.txt or_integration_tests(PASSFAIL_TESTS
@@ -104,6 +105,10 @@ filegroup(
104105
) + {
105106
"ext_pattern": ["generate_pattern.defok"],
106107
"gcd": ["ext_pattern.rules"],
108+
"no_merging": [
109+
"ext_pattern.rules",
110+
"gcd.def",
111+
],
107112
}.get(test_name, []),
108113
)
109114
for test_name in ALL_TESTS

src/rcx/test/CMakeLists.txt

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ or_integration_tests(
88
names
99
net_name_consistency
1010
coordinates
11+
no_merging
1112
PASSFAIL_TESTS
1213
rcx_unit_test
1314
)

src/rcx/test/no_merging.ok

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
[INFO ODB-0227] LEF file: sky130hs/sky130hs.tlef, created 13 layers, 25 vias
2+
[INFO ODB-0227] LEF file: sky130hs/sky130hs_std_cell.lef, created 390 library cells
3+
[INFO ODB-0128] Design: gcd
4+
[INFO ODB-0130] Created 54 pins.
5+
[INFO ODB-0131] Created 8171 components and 33894 component-terminals.
6+
[INFO ODB-0132] Created 2 special nets and 0 connections.
7+
[INFO ODB-0133] Created 411 nets and 1210 connections.
8+
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
9+
[INFO RCX-0029] Defined extraction corner X
10+
[INFO RCX-0435] Reading extraction model file ext_pattern.rules ...
11+
[INFO RCX-0436] RC segment generation gcd (max_merge_res 0.0) ...
12+
[INFO RCX-0040] Final 4791 rc segments
13+
[INFO RCX-0439] Coupling Cap extraction gcd ...
14+
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
15+
[INFO RCX-0442] 50% of 2368 wires extracted
16+
[INFO RCX-0442] 100% of 2368 wires extracted
17+
[INFO RCX-0045] Extract 411 nets, 5202 rsegs, 5202 caps, 2237 ccs
18+
[INFO RCX-0443] 411 nets finished
19+
No differences found.

0 commit comments

Comments
 (0)