Merge pull request #601 from Strykar/main

drivers/video: Improve IT66021 EDID definitions and add new DTDs

Author: ligenxxxx

src/driver/it66021.c

@@ -232,7 +232,7 @@ int IT66021_Get_VTMG(int *freq_ref) {
     }
 
     for (i = 0; i < IT66121_9A_READ_N; i++) {
-        for (j = IT66121_9A_READ_N - 1; j >= i; j--) {
+        for (j = IT66121_9A_READ_N - 2; j >= i; j--) {
             if (r9a[j] > r9a[j + 1]) {
                 int temp = r9a[j];
                 r9a[j] = r9a[j + 1];
@@ -307,34 +307,63 @@ void IT66021_Set_CSMatrix(int cs) {
 }
 
 void IT66021_edid() {
-    // 0x49->0xc4 must set same data with edid[0x7f]
-    // 0x49->0xc5 must set same data with edid[0xff]
-    const uint8_t edid[256] = {
-        0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x26, 0x85, 0x02, 0x66, 0x01, 0x68, 0x00, 0x00,
-        0x00, 0x17, 0x01, 0x03, 0x80, 0x73, 0x41, 0x78, 0x2A, 0x7C, 0x11, 0x9E, 0x59, 0x47, 0x9B, 0x27,
-        0x10, 0x50, 0x54, 0x00, 0x00, 0x00, 0x81, 0xC0, 0x81, 0xE8, 0xD1, 0xC0, 0x01, 0x01, 0x01, 0x01,
-        0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A, 0x80, 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x58, 0x2C,
-        0x45, 0x00, 0x10, 0x09, 0x00, 0x00, 0x00, 0x1E, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
-        0x6E, 0x28, 0x55, 0x00, 0x10, 0x09, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x49,
-        0x54, 0x45, 0x36, 0x38, 0x30, 0x32, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xFD,
-        0x00, 0x30, 0x7A, 0x0F, 0x50, 0x10, 0x00, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x2C,
-        0x02, 0x03, 0x17, 0x74, 0x44, 0x84, 0x9F, 0xA9, 0x90, 0x23, 0x09, 0x07, 0x07, 0x83, 0x01, 0x00,
-        0x00, 0x65, 0x03, 0x0C, 0x00, 0x10, 0x00, 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20, 0x6E,
-        0x28, 0x55, 0x00, 0x10, 0x09, 0x00, 0x00, 0x00, 0x1E, 0x02, 0x3A, 0x80, 0xD0, 0x72, 0x38, 0x2D,
-        0x40, 0x58, 0x2C, 0x45, 0x00, 0x10, 0x09, 0x00, 0x00, 0x00, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDA};
+    // Declared as static to prevent 256-byte stack allocation overhead
+    static const uint8_t edid[256] = {
+        /* ===== Base EDID block (0x00–0x7F) ===== */
+        0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,
+        0x26,0x85,0x02,0x66,0x01,0x68,0x00,0x00,
+        0x00,0x17,0x01,0x03,0x80,0x73,0x41,0x78,
+        0x2A,0x7C,0x11,0x9E,0x59,0x47,0x9B,0x27,
+        0x10,0x50,0x54,0x00,0x00,0x00,0x81,0xC0,
+        0x81,0xE8,0xD1,0xC0,0x01,0x01,0x01,0x01,
+        0x01,0x01,0x01,0x01,0x01,0x01,
+        /* DTD #1: 1920x1080 @ 60 Hz */
+        0x02,0x3A,0x80,0xD0,0x72,0x38,0x2D,0x40,
+        0x58,0x2C,0x45,0x00,0x10,0x09,0x00,0x00,
+        0x00,0x1E,
+        /* DTD #2: 1280x720 @ 60 Hz */
+        0x01,0x1D,0x00,0x72,0x51,0xD0,0x1E,0x20,
+        0x6E,0x28,0x55,0x00,0x10,0x09,0x00,0x00,
+        0x00,0x18,
+        /* Monitor name */
+        0x00,0x00,0x00,0xFC,0x00,
+        0x49,0x54,0x45,0x36,0x38,0x30,0x32,0x0A,
+        0x20,0x20,0x20,0x20,0x20,
+        /* Range limits */
+        0x00,0x00,0x00,0xFD,0x00,
+        0x30,0x7A,0x0F,0x50,0x10,0x00,0x0A,
+        0x20,0x20,0x20,0x20,0x20,0x20,
+        /* Extension count */
+        0x01,
+        /* Base EDID checksum (sum of bytes 0x00–0x7E == 0 mod 256) */
+        /* Base EDID checksum explicitly pinned to byte 127 */
+        [127] = 0x2C,
+        /* ===== CEA Extension block (0x80–0xFF) ===== */
+        /* CEA extension checksum (sum of bytes 0x80–0xFE == 0 mod 256) */
+        /* C99 index 128 follows directly after 127 */
+        0x02,0x03,0x17,0x74,
+        0x44,0x84,0x9F,0xA9,0x90,0x23,0x09,0x07,
+        0x07,0x83,0x01,0x00,
+        0x00,0x65,0x03,0x0C,0x00,0x10,0x00,
+        /* DTD #3: 1280x720 @ 50 Hz */
+        0x29,0x1D,0x00,0x72,0x51,0xD0,0x1E,0x20,
+        0x6E,0x28,0x55,0x00,0x10,0x09,0x00,0x00,
+        0x00,0x1E,
+        /* DTD #4: 960x720 @ 100 Hz (CVT-RB) */
+        0x00,0x60,0x80,0x18,0x71,0x38,0x2D,0x40,
+        0x58,0x2C,0x45,0x00,0x10,0x09,0x00,0x00,
+        0x00,0x1E,
+        /* C compiler automatically supplies 0x00 padding for the gap here */
+        /* Extension checksum explicitly pinned to the final byte */
+        [255] = 0x47
+    };
     uint16_t i;
     I2C_L_Write(0x49, 0xc0, 0x40);
     I2C_L_Write(0x49, 0xc4, edid[0x7f]);
     I2C_L_Write(0x49, 0xc5, edid[0xff]);
-
     for (i = 0; i < 256; i++) {
         I2C_L_Write(0x54, i, edid[i]);
     }
-
     I2C_L_Write(0x49, 0xc0, 0x24);
     usleep(2000);
     I2C_L_Write(0x49, 0xc0, 0x04);
@@ -346,4 +375,4 @@ void IT66021_Set_Pclk(int inv, int dly) {
         I2C_L_Write(ADDR_IT66021, 0x50, 0xA0 + dly);
     else
         I2C_L_Write(ADDR_IT66021, 0x50, 0xB0 + dly);
-}
+}