diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts index 8d87a78bd8782..188d3640147e1 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -25,6 +25,56 @@ stdout-path = "serial0:115200n8"; }; + sound { + compatible = "qcom,shikra-sndcard"; + qcom,tdm-slots = <2>; + qcom,tdm-slot-width = <32>; + qcom,tdm-codec-slot-mask = <0x03>; + + clocks = <&q6prmcc QAIF_CLK_ID_AUD_INTF2_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "aud-intf2-ibit"; + + pinctrl-0 = <&i2s2_default>, <&dmic_eldo_en_defualt>; + pinctrl-names = "default"; + model = "shikra-cqs-evk"; + + audio-routing = "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + va-dmic-dai-link { + link-name = "VA DMIC Capture"; + + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + codec { + sound-dai = <&vamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-playback-dai-link { + link-name = "WSA Playback"; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_TDM_RX_0>; + }; + + codec { + sound-dai = <&wsa885x_i2c>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; lcd_bias: regulator-lcd-bias { compatible = "regulator-fixed"; regulator-name = "lcd_bias"; @@ -76,6 +126,59 @@ }; }; +&audiocorecc { + compatible = "qcom,shikra-cqs-audiocorecc"; +}; + +&i2c3 { + status = "okay"; + + wsa885x_i2c: wsa885x-i2c-codec@c { + compatible = "qcom,wsa885x-i2c"; + reg = <0x0c>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa885x_i2c_spkr_sd_n>; + + interrupt-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + vdd-1p8-supply = <&pm4125_l15>; + vdd-io-supply = <&pm4125_l15>; + qcom,battery_config = <2>; + + wsa885x-init-table = + <0x8470 0x2 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_CLR(1) */ + 0x8470 0x0 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_CLR(0) */ + 0x8470 0x1 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_EN(1) */ + 0x0004 0x1 /* SMP_AMP_CTRL_STEREO_CMT_GRP_MASK - CMT_GRP_MASK(1) */ + 0x8602 0x60 /* CDC_RX0_RX_PATH_CFG1 - HPF_EN(0) */ + 0x8622 0x60 /* CDC_RX1_RX_PATH_CFG1 - HPF_EN(0) */ + 0x8458 0x79 /* PANDEIRO_DIG_CTRL0_VBAT_THRM_FLT_CTL - VBAT_COEF_SEL */ + 0x810B 0xD9 /* PANDEIRO_ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3 */ + 0x8111 0xD9 /* PANDEIRO_ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3 */ + 0x813C 0x08 /* SPK_TOP_COMMON_CTRL4 - override_ctl*/ + 0x8102 0x04 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_COMMON_CTRL2.LDO_PROG */ + 0x811C 0x29 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_LF_CH1_CTRL11.PHASE90(Add 90 degree phase shift between PWM clock of CH1 and CH2.) */ + 0x811D 0x40 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH1_TUNE1 - HIZ_DELAY_PROG*/ + 0x8129 0x40 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH2_TUNE1 - HIZ_DELAY_PROG*/ + 0x811A 0x80 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH1_CTRL9 - OCP_CLIP_T_CTRL_EXT */ + 0x8126 0x80 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH2_CTRL9 - OCP_CLIP_T_CTRL_EXT */ + 0x8103 0x6 /* PANDEIRO_ANA_TOP_SPK_TOP_COMMON_TUNE1 - GAIN_TUNE */ + 0x80CA 0x85 /* PANDEIRO_ANA_TOP_IVSENSE_ADC_MODE_CTL2 - SPARE_BITS_0(Sets LDO to 1.6V) */ + 0x80CB 0xE /* PANDEIRO_ANA_TOP_IVSENSE_ADC_MODE_CTL3 - ADC_VREF_VCTL_I(Sets VREF_I to 1.35V) */ + 0x80CC 0xC /* PANDEIRO_ANA_TOP_IVSENSE_ADC_REF_CTL - ADC_VREF_VCTL_V(Sets VREF_V to 1.35V) */ + 0x80D0 0x80 /* PANDEIRO_ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2 */ + 0x80BA 0xC0 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_SPARE3(force the VDDSPK_LV_READY from analog to be high) */ + 0x841C 0x4E /* PANDEIROI2S.TOP.PANDEIRO_DIG_CTRL0_PANDEIRO_DIG_CTRL0.CDC_CLK_CTL.FSM_INTP_CG_DISABLE */ + 0x8435 0x47 /* PANDEIRO_DIG_CTRL0_PA1_FSM_CTL1 - SILENT_STATE_IVS_EN */ + 0x86CE 0x09 /* PANDEIROI2S.TOP.CDC_CLSH_CDC_CLSH.V1P8_BP_CTL2.BP_CNT */ + 0x8667 0x34 /* CDC_COMPANDER1_CTL7 - AGAIN_DELAY */ + 0x800D 0x08>; /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.PON_CKSK_CTL_0 */ + + #sound-dai-cells = <0>; + }; +}; + &mdss_dsi0_out { remote-endpoint = <&panel_in>; data-lanes = <0 1 2 3>; @@ -114,9 +217,20 @@ }; &remoteproc_mpss { - firmware-name = "qcom/shikra/qdsp6sw.mbn"; + firmware-name = "qcom/shikra/qdsp6sw.mbn"; - status = "okay"; + status = "okay"; +}; + +&rxmacro { + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", + "npl", + "fsgen"; + + status = "okay"; }; &sdhc_1 { @@ -151,7 +265,114 @@ status = "okay"; }; +&spmi_bus { + pmic@0 { + pmic4125_codec: audio-codec@f000 { + compatible = "qcom,pm4125-codec"; + reg = <0xf000>; + vdd-io-supply = <&pm4125_l15>; + vdd-cp-supply = <&pm4125_s1>; + vdd-pa-vpos-supply = <&pm4125_s1>; + + vdd-mic-bias-supply = <&pm4125_l22>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + + qcom,rx-device = <&pm4125_rx>; + qcom,tx-device = <&pm4125_tx>; + #sound-dai-cells = <1>; + + status = "okay"; + }; + }; +}; + +&swr1 { + status = "okay"; + + pm4125_tx: codec@0,3 { + compatible = "sdw20217010c00"; + reg = <0 3>; + qcom,tx-port-mapping = <2 2 3 4>; + }; +}; + +&swr0 { + status = "okay"; + + pm4125_rx: codec@0,4 { + compatible = "sdw20217010c00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5 >; + }; +}; + &tlmm { + dmic01_default: dmic01-default-state { + clk-pins { + pins = "gpio96"; + function = "dmic"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio97"; + function = "dmic"; + drive-strength = <8>; + input-enable; + }; + }; + + dmic23_default: dmic23-default-state { + clk-pins { + pins = "gpio98"; + function = "dmic"; + drive-strength = <8>; + output-high; + }; + + data-pins { + pins = "gpio99"; + function = "dmic"; + drive-strength = <8>; + input-enable; + }; + }; + dmic_eldo_en_defualt: dmic_eldo_en_default { + pins = "gpio71"; + function = "gpio"; + drive-strength = <8>; /* 8 mA */ + bias-disable; + output-high; + }; + + i2s2_default: i2s2-default-active-state { + pins = "gpio100", "gpio101", "gpio102", "gpio103"; + function = "i2s2"; + drive-strength = <8>; + bias-disable; + }; + + i2s2_sleep: i2s2-sleep-state { + pins = "gpio100", "gpio101", "gpio102", "gpio103"; + function = "i2s2"; + drive-strength = <2>; + bias-disable; + }; + + wsa885x_i2c_spkr_sd_n: wsa885x-i2c-spkr-sd-n-active-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <8>; + input-disable; + output-enable; + }; lcd_bias_en: lcd-bias-en-state { pins = "gpio151"; function = "gpio"; @@ -225,6 +446,18 @@ remote-endpoint = <&pm4125_ss_in>; }; +&vamacro { + pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&swr_tx_clk>, <&swr_tx_data0>; + pinctrl-names = "default"; + + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "npl"; + + qcom,dmic-sample-rate = <4800000>; + status = "okay"; +}; + &wifi { vdd-0.8-cx-mx-supply = <&pm4125_l7>; vdd-1.8-xo-supply = <&pm4125_l13>; @@ -235,4 +468,3 @@ status = "okay"; }; - diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index bc6728eec8994..3644d56b4648c 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -3,19 +3,22 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ -#include #include +#include #include #include #include #include +#include +#include #include #include -#include #include #include #include #include +#include +#include #include / { @@ -997,6 +1000,41 @@ drive-strength = <2>; bias-pull-up; }; + + swr_rx_clk: swr-rx-clk { + pins = "gpio107"; + function = "swr0_rx"; + drive-strength = <8>; + bias-disable; + }; + + swr_rx_data0: swr-rx-data0 { + pins = "gpio108"; + function = "swr0_rx"; + drive-strength = <8>; + bias-bus-hold; + }; + + swr_rx_data1: swr-rx-data1 { + pins = "gpio109"; + function = "swr0_rx"; + drive-strength = <8>; + bias-bus-hold; + }; + + swr_tx_clk: swr-tx-clk { + pins = "gpio105"; + function = "swr0_tx"; + drive-strength = <8>; + bias-disable; + }; + + swr_tx_data0: swr-tx-data0 { + pins = "gpio106"; + function = "swr0_tx"; + drive-strength = <8>; + bias-bus-hold; + }; }; pmu@c91000 { @@ -3018,6 +3056,40 @@ mboxes = <&apcs_glb 12>; qcom,remote-pid = <1>; label = "mpss"; + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "modem_apps"; + qcom,domain = ; + qcom,intents = <200 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + compatible = "qcom,q6apm"; + reg = ; + #sound-dai-cells = <0>; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + qcom,vmid = ; + }; + }; + + q6prm: service@2 { + compatible = "qcom,q6prm"; + reg = ; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; }; }; @@ -4402,6 +4474,116 @@ }; }; + rxmacro: codec@A040000 { + compatible = "qcom,shikra-lpass-rx-macro"; + reg = <0x0 0x0a040000 0x0 0x1000>; + + pinctrl-0 = <&swr_rx_clk>, <&swr_rx_data0>, <&swr_rx_data1>; + pinctrl-names = "default"; + + clocks = <&audiocorecc AUDIO_CORE_CC_RX_MCLK_CLK>, + <&audiocorecc AUDIO_CORE_CC_RX_MCLK_2X_CLK>, + <&vamacro>; + clock-names = "mclk", + "npl", + "fsgen"; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + status = "disabled"; + }; + + swr0: soundwire@a060000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0x0 0x0a060000 0x0 0x10000>; + qcom,swr-master-ee-val = <0>; + + interrupts = ; + + clocks = <&rxmacro>; + clock-names = "iface"; + + label = "RX"; + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + resets = <&audiocorecc AUDIO_CORE_CSR_RX_SWR_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + + vamacro: codec@a078000 { + compatible = "qcom,shikra-lpass-va-macro"; + reg = <0x0 0x0a078000 0x0 0x2000>; + + pinctrl-0 = <&swr_tx_clk>, <&swr_tx_data0>; + pinctrl-names = "default"; + + clocks = <&audiocorecc AUDIO_CORE_CC_TX_MCLK_CLK>, + <&audiocorecc AUDIO_CORE_CC_TX_MCLK_2X_CLK>; + clock-names = "mclk", + "npl"; + + #clock-cells = <0>; + #sound-dai-cells = <1>; + clock-output-names = "fsgen"; + status = "disabled"; + }; + + swr1: soundwire@a080000 { + compatible = "qcom,soundwire-v3.1.0"; + reg = <0x0 0x0a080000 0x0 0x10000>; + qcom,swr-master-ee-val = <0>; + + interrupts = , + ; + interrupt-names = "core", "wakeup"; + + clocks = <&vamacro>; + clock-names = "iface"; + + label = "VA_TX"; + + qcom,din-ports = <3>; + qcom,dout-ports = <0>; + + resets = <&audiocorecc AUDIO_CORE_CSR_TX_SWR_CGCR>; + reset-names = "swr_audio_cgcr"; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control = /bits/ 8 <0x00 0x00 0x00>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + + status = "disabled"; + }; + epss_l3: interconnect@fd90000 { compatible = "qcom,shikra-epss-l3"; reg = <0x0 0x0fd90000 0x0 0x1000>; diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h index 45850f2d43425..ef920e335dfac 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -239,6 +239,35 @@ #define Q6AFE_MAX_CLK_ID 104 +#define QAIF_CLK_ID_AUD_INTF0_IBIT 104 +#define QAIF_CLK_ID_AUD_INTF0_EBIT 105 +#define QAIF_CLK_ID_AUD_INTF1_IBIT 106 +#define QAIF_CLK_ID_AUD_INTF1_EBIT 107 +#define QAIF_CLK_ID_AUD_INTF2_IBIT 108 +#define QAIF_CLK_ID_AUD_INTF2_EBIT 109 +#define QAIF_CLK_ID_AUD_INTF3_IBIT 110 +#define QAIF_CLK_ID_AUD_INTF3_EBIT 111 +#define QAIF_CLK_ID_AUD_INTF4_IBIT 112 +#define QAIF_CLK_ID_AUD_INTF4_EBIT 113 +#define QAIF_CLK_ID_AUD_INTF5_IBIT 114 +#define QAIF_CLK_ID_AUD_INTF5_EBIT 115 +#define QAIF_CLK_ID_AUD_INTF6_IBIT 116 +#define QAIF_CLK_ID_AUD_INTF6_EBIT 117 +#define QAIF_CLK_ID_AUD_INTF7_IBIT 118 +#define QAIF_CLK_ID_AUD_INTF7_EBIT 119 +#define QAIF_CLK_ID_AUD_INTF8_IBIT 120 +#define QAIF_CLK_ID_AUD_INTF8_EBIT 121 +#define QAIF_CLK_ID_AUD_INTF9_IBIT 122 +#define QAIF_CLK_ID_AUD_INTF9_EBIT 123 +#define QAIF_CLK_ID_AUD_INTF10_IBIT 124 +#define QAIF_CLK_ID_AUD_INTF10_EBIT 125 +#define QAIF_CLK_ID_AUD_INTF11_IBIT 126 +#define QAIF_CLK_ID_AUD_INTF11_EBIT 127 +#define QAIF_CLK_ID_AUD_INTF12_IBIT 128 +#define QAIF_CLK_ID_AUD_INTF12_EBIT 129 +#define QAIF_CLK_ID_AUD_VA_INTF0_IBIT 130 +#define QAIF_CLK_ID_AUD_VA_INTF0_EBIT 131 + #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 #define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2