From 6df93d23f6e913f3cd2275cd198b8cb0e45068ab Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Wed, 27 May 2026 19:56:09 +0530 Subject: [PATCH 1/2] arm64: dts: qcom: shikra: Update SDHC power and interconnect tags Update the SDHC node to align with the RPM-based architecture of the Shikra platform for eMMC device: - Replace generic interconnect tags with RPM_ALWAYS_TAG and RPM_ACTIVE_TAG. - Switch the power domain from RPMh-based RPMHPD_CX to RPMPD-based QCM2290_VDDCX. - Update the 384 MHz OPP voltage requirement from NOM to SVS_PLUS to optimally match the official clock plan. Signed-off-by: Monish Chunara --- arch/arm64/boot/dts/qcom/shikra.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index bc6728eec899..a0e2679926a8 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1308,14 +1308,14 @@ "core", "xo"; - interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, - <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; interconnect-names = "sdhc-ddr", "cpu-sdhc"; - power-domains = <&rpmpd RPMHPD_CX>; + power-domains = <&rpmpd QCM2290_VDDCX>; operating-points-v2 = <&sdhc1_opp_table>; qcom,dll-config = <0x000f642c>; @@ -1345,7 +1345,7 @@ opp-384000000 { opp-hz = /bits/ 64 <384000000>; - required-opps = <&rpmpd_opp_nom>; + required-opps = <&rpmpd_opp_svs_plus>; opp-peak-kBps = <800000 300000>; opp-avg-kBps = <400000 0>; }; From 1626d1538f9bd8fb02d7bb7848b3de8147d45e6d Mon Sep 17 00:00:00 2001 From: Monish Chunara Date: Wed, 27 May 2026 20:06:17 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: shikra: Update SDHC2 power and interconnects Add the QCM2290_VDDCX power domain and update interconnect tags to RPM-specific macros for SDHC2 to align with the Shikra platform architecture. Update the 202 MHz OPP to require the optimal voltage corner per the official hardware clock plan. Signed-off-by: Monish Chunara --- arch/arm64/boot/dts/qcom/shikra.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index a0e2679926a8..36de53849465 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -1367,15 +1367,16 @@ <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + power-domains = <&rpmpd QCM2290_VDDCX>; qcom,dll-config = <0x0007442c>; qcom,ddr-config = <0x80040868>; iommus = <&apps_smmu 0x0a0 0x0>; - interconnects = <&system_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS - &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, - <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY - &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_SDCC_2 RPM_ACTIVE_TAG>; interconnect-names = "sdhc-ddr","cpu-sdhc"; operating-points-v2 = <&sdhc2_opp_table>; @@ -1391,7 +1392,7 @@ opp-202000000 { opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmpd_opp_nom>; + required-opps = <&rpmpd_opp_svs_plus>; }; }; };