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68kDisassembler_Sub_EA.L68
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277 lines (273 loc) · 19 KB
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00001000 Starting Address
Assembler used: EASy68K Editor/Assembler v5.16.01
Created On: 11/27/2021 21:42:23
00000000 1 *-----------------------------------------------------------
00000000 2 * Title : 68k Disassembler EA Decoding Subroutine
00000000 3 * Written by : Zach Hanneman
00000000 4 * Date : 11/27/21
00000000 5 * Description: This subroutine aims to handle the EA decoding
00000000 6 * portion of the 68k disassembler program. It expects the
00000000 7 * data detailed below this description as parameters in order
00000000 8 * to handle the decoding of the Effective Address Mode portion
00000000 9 * of the instruction currently being disassembled by the program.
00000000 10 * One run of this subroutine corresponds to a single operand to process.
00000000 11 *
00000000 12 * PRECONDITIONS:
00000000 13 * D5: A number representing the size of the instruction, as follows: (Needed for #<data> case, since we don't know how much data to grab otherwise!)
00000000 14 * * Not Set = 0 (or anything else, really. Always set when possible!)
00000000 15 * * .B = 1
00000000 16 * * .W = 2
00000000 17 * * .L = 3
00000000 18 * D6: The 6-bit <ea> field (two most significant bits cleared to 0s)
00000000 19 * A5: Address of next word to decode (Assumed already at position after opcode word being decoded)
00000000 20 * A6: Print Buffer at next available space (If we end up using this...)
00000000 21 *
00000000 22 * POSTCONDITIONS:
00000000 23 * D7: Good/Bad flag; Remains the same unless error occurred (e.g. invalid mode)
00000000 24 * A5: Memory pointer at the next opcode word (only modified if operation involved data or absolute address modes)
00000000 25 * A6: Pointer to next free space in print buffer (if we end up using it...)
00000000 26 *-----------------------------------------------------------
00001000 27 START ORG $1000 * TEMP: REMOVE ON INTEGRATION ****
00001000 28 *------------*TESTING CODE: RM ON INTEGRATION*--------------
00001000 29
00001000 30 * Define anything I need for unit testing in here:
00001000 31 * 6-bit <ea> field (FORMAT: MODE, then REG)
00001000 32 * Sample current memory address word location in A5
00001000 33 * Sample print buffer (? - May not be using, we'll see during integration)
00001000 34
00001000 4BF8 1006 35 LEA $1006,A5 * TEST: Dummy "next opcode word" value. (corresponds to opcode after the instruction after this)
00001004 303C 78F0 36 MOVE.W #$78F0,D0 * TEST: Sample instruction for EA modes needing to incr. A5 (immediate address & abs address)
00001008 37 * Otherwise, points to some data corresponding to opcode!
00001008 38 * Test inserted vals here...
00001008 39
00001008 1C3C 003C 40 MOVE.B #%00111100,D6 * TEST: <ea> BITFIELD AT D6
0000100C 1A3C 0002 41 MOVE.B #2,D5 * TEST: SIZE VALUE OF INSTRUCTION (see above correspondences; only used for #<data>)
00001010 42
00001010 43 *-------------------Program Code----------------------------
00001010 44 * 1: Process the 6-bit field into D3 (Register bits) and D4 (Mode bits)
00001010 1806 45 MOVE.B D6,D4 * Prime D4 with the full 6-bit field
00001012 C83C 0007 46 AND.B #%00000111,D4 * Clear everything but the register bits (BITS READY)
00001016 47
00001016 1606 48 MOVE.B D6,D3 * Prime D3 with the full 6-bit field
00001018 E60B 49 LSR.B #3,D3 * Shift out the register bits to isolate the mode bits (BITS READY)
0000101A 50
0000101A 51 * 2: Process the MODE BITS:
0000101A B63C 0000 52 MODE_P CMP.B #%00000000,D3 * TEST FOR 000: Dn
0000101E 6700 002E 53 BEQ DN_MODE
00001022 54
00001022 B63C 0001 55 CMP.B #%00000001,D3 * TEST FOR 001: An
00001026 6700 0036 56 BEQ AN_MODE
0000102A 57
0000102A B63C 0002 58 CMP.B #%00000010,D3 * TEST FOR 010: (An)
0000102E 6700 003E 59 BEQ ANIND_MODE
00001032 60
00001032 B63C 0003 61 CMP.B #%00000011,D3 * TEST FOR 011: (An)+
00001036 6700 0046 62 BEQ ANINC_MODE
0000103A 63
0000103A B63C 0004 64 CMP.B #%00000100,D3 * TEST FOR 100: -(An)
0000103E 6700 004E 65 BEQ ANDEC_MODE
00001042 66
00001042 B63C 0007 67 CMP.B #%00000111,D3 * TEST FOR 111: #<data>, (xxx).W, or (xxx).L (or unsupported!)
00001046 6700 0056 68 BEQ ABSDAT_MODE
0000104A 69
0000104A 6000 012A 70 BRA UNSUPP_MODE * If we made it here, assume an unsupported mode!
0000104E 71
0000104E 72
0000104E 43F9 0000118A 73 DN_MODE LEA PRNT_D,A1
00001054 103C 000E 74 MOVE.B #14,D0
00001058 4E4F 75 TRAP #15
0000105A 76
0000105A 6000 005E 77 BRA REG_P
0000105E 78
0000105E 43F9 0000118C 79 AN_MODE LEA PRNT_A,A1
00001064 103C 000E 80 MOVE.B #14,D0
00001068 4E4F 81 TRAP #15
0000106A 82
0000106A 6000 004E 83 BRA REG_P
0000106E 84
0000106E 43F9 0000118E 85 ANIND_MODE LEA PRNT_AI,A1
00001074 103C 000E 86 MOVE.B #14,D0
00001078 4E4F 87 TRAP #15
0000107A 88
0000107A 6000 003E 89 BRA REG_P
0000107E 90
0000107E 43F9 0000118E 91 ANINC_MODE LEA PRNT_AI,A1 * As of now this is the same as indirect, postdec added after register
00001084 103C 000E 92 MOVE.B #14,D0
00001088 4E4F 93 TRAP #15
0000108A 94
0000108A 6000 002E 95 BRA REG_P
0000108E 96
0000108E 43F9 00001196 97 ANDEC_MODE LEA PRNT_DC,A1
00001094 103C 000E 98 MOVE.B #14,D0
00001098 4E4F 99 TRAP #15
0000109A 100
0000109A 6000 001E 101 BRA REG_P
0000109E 102
0000109E 103
0000109E 104 * DATA / ABSOLUTE ADDRESSING HANDLING (Mode was 111 in D3; need to chk. D4 reg bits for behavior)
0000109E B83C 0004 105 ABSDAT_MODE CMP.B #%00000100,D4 * TEST FOR 100: #<data>
000010A2 6700 005A 106 BEQ DATA_MODE
000010A6 107
000010A6 B83C 0000 108 CMP.B #%00000000,D4 * TEST FOR 000: (xxx).W
000010AA 6700 0076 109 BEQ ABSW_MODE
000010AE 110
000010AE B83C 0001 111 CMP.B #%00000001,D4 * TEST FOR 001: (xxx).L
000010B2 6700 007E 112 BEQ ABSL_MODE
000010B6 113
000010B6 6000 00BE 114 BRA UNSUPP_MODE * If the register is some other val, unsupported!
000010BA 115
000010BA 116 * 3: Process the REGISTER BITS: (IN D4)
000010BA 1204 117 REG_P MOVE.B D4,D1 * Load the register value into D1 for display.
000010BC 103C 0003 118 MOVE.B #3,D0
000010C0 4E4F 119 TRAP #15
000010C2 120
000010C2 B63C 0002 121 CMP.B #%00000010,D3
000010C6 6700 0016 122 BEQ END_ONE
000010CA 123
000010CA B63C 0004 124 CMP.B #%00000100,D3
000010CE 6700 000E 125 BEQ END_ONE
000010D2 126
000010D2 B63C 0003 127 CMP.B #%00000011,D3
000010D6 6700 0016 128 BEQ END_TWO
000010DA 129
000010DA 6000 00AA 130 BRA FINISH * Additional char after register unnecessary, branch to finish
000010DE 131
000010DE 43F9 00001191 132 END_ONE LEA PRNT_CL,A1
000010E4 103C 000E 133 MOVE.B #14,D0
000010E8 4E4F 134 TRAP #15
000010EA 135
000010EA 6000 009A 136 BRA FINISH
000010EE 137
000010EE 43F9 00001193 138 END_TWO LEA PRNT_IN,A1
000010F4 103C 000E 139 MOVE.B #14,D0
000010F8 4E4F 140 TRAP #15
000010FA 141
000010FA 6000 008A 142 BRA FINISH
000010FE 143
000010FE 144 * #<DATA>; RELIES ON D5 CONTAINING SIZE VALUE OF THE INSTRUCTION! (So we know how much data to grab, then what to increment A5 by! (word or long))
000010FE 145 * If this contains 0, this will not work in this state. D5 MUST have val 1-3 at this point!
000010FE 43F9 0000119A 146 DATA_MODE LEA PRNT_DT,A1 * Print '#$'
00001104 103C 000E 147 MOVE.B #14,D0
00001108 4E4F 148 TRAP #15
0000110A 149
0000110A BA3C 0001 150 CMP.B #1,D5
0000110E 6700 0032 151 BEQ BYTE
00001112 152
00001112 BA3C 0002 153 CMP.B #2,D5
00001116 6700 003E 154 BEQ WORD
0000111A 155
0000111A BA3C 0003 156 CMP.B #3,D5
0000111E 6700 0046 157 BEQ LONG
00001122 158
00001122 159 * (xxx).W;
00001122 43F9 0000119D 160 ABSW_MODE LEA PRNT_HX,A1 * Print '$'
00001128 103C 000E 161 MOVE.B #14,D0
0000112C 4E4F 162 TRAP #15
0000112E 163
0000112E 6000 0026 164 BRA WORD
00001132 165
00001132 166 * (xxx).L; Assembler uses this when it sign extends automatically over (xxx).W
00001132 43F9 0000119D 167 ABSL_MODE LEA PRNT_HX,A1 * Print '$'
00001138 103C 000E 168 MOVE.B #14,D0
0000113C 4E4F 169 TRAP #15
0000113E 170
0000113E 6000 0026 171 BRA LONG
00001142 172
00001142 173 * Expects format created by assembled machine code, NOT how it is just pushed to memory by (An)!
00001142 321D 174 BYTE MOVE.W (A5)+,D1 * Move word of data from curr opcode word pointer to D1, then increment pointer a word.
00001144 143C 0010 175 MOVE.B #16,D2 * Prepare to display a hex value
00001148 176
00001148 C27C 00FF 177 AND.W #%0000000011111111,D1 * Discard potential word part from byte
0000114C 103C 000F 178 MOVE.B #15,D0 * Set the task to 15
00001150 4E4F 179 TRAP #15 * Print the value.
00001152 180
00001152 6000 0032 181 BRA FINISH
00001156 182
00001156 321D 183 WORD MOVE.W (A5)+,D1 * Move word of data from curr opcode word pointer to D1, then increment pointer a word.
00001158 143C 0010 184 MOVE.B #16,D2 * Prepare to display a hex value
0000115C 185
0000115C 103C 000F 186 MOVE.B #15,D0 * Set the task to 15
00001160 4E4F 187 TRAP #15 * Print the value.
00001162 188
00001162 6000 0022 189 BRA FINISH
00001166 190
00001166 221D 191 LONG MOVE.L (A5)+,D1 * Move longword of data from curr opcode word pointer to D1, then increment pointer a longword.
00001168 143C 0010 192 MOVE.B #16,D2 * Prepare to display a hex value
0000116C 193
0000116C 103C 000F 194 MOVE.B #15,D0 * Set the task to 15
00001170 4E4F 195 TRAP #15 * Print the value.
00001172 196
00001172 6000 0012 197 BRA FINISH
00001176 198
00001176 199 * 4: UNSUPPORTED BRANCH:
00001176 43F9 0000119F 200 UNSUPP_MODE LEA PRNT_ER,A1
0000117C 103C 000E 201 MOVE.B #14,D0
00001180 4E4F 202 TRAP #15 * Continue directly onto finishing up from here
00001182 203
00001182 1E3C 0000 204 MOVE.B #0,D7 * Set Good/Bad flag to Bad state (0 bit)
00001186 205
00001186 206 * 5: Finishing up:
00001186 207 FINISH
00001186 208 * Return values stored in stack prior to moving into here into registers.
00001186 209 * (Will put here on integration...)
00001186 210 * A5 currently points to the next needed opcode to process, which could be the following:
00001186 211 * Next opcode word instruction
00001186 212 * More data corresponding to the next <ea> field for current instruction
00001186 213
00001186 FFFF FFFF 214 SIMHALT * TEMP: REMOVE ON INTEGRATION **********
0000118A 215 *------------------Vars and Consts--------------------------
0000118A 216
0000118A 217 * Define any constants/vars besides registers I need here.
0000118A 218
0000118A 219 *------------------Messages for Printing -------------------
0000118A =0000000D 220 CR EQU $0D
0000118A =0000000A 221 LF EQU $0A
0000118A 222
0000118A= 44 00 223 PRNT_D DC.B 'D',0
0000118C= 41 00 224 PRNT_A DC.B 'A',0
0000118E= 28 41 00 225 PRNT_AI DC.B '(A',0
00001191= 29 00 226 PRNT_CL DC.B ')',0
00001193= 29 2B 00 227 PRNT_IN DC.B ')+',0
00001196= 2D 28 41 00 228 PRNT_DC DC.B '-(A',0
0000119A 229
0000119A= 23 24 00 230 PRNT_DT DC.B '#$',0
0000119D= 24 00 231 PRNT_HX DC.B '$',0
0000119F 232
0000119F= 45 52 52 4F 52 3A ... 233 PRNT_ER DC.B 'ERROR: Unsupported EA Mode',0
000011BA 234 *-----------------------------------------------------------
000011BA 235 END START * TEMP: REMOVE ON INTEGRATION *****
No errors detected
No warnings generated
SYMBOL TABLE INFORMATION
Symbol-name Value
-------------------------
ABSDAT_MODE 109E
ABSL_MODE 1132
ABSW_MODE 1122
ANDEC_MODE 108E
ANINC_MODE 107E
ANIND_MODE 106E
AN_MODE 105E
BYTE 1142
CR D
DATA_MODE 10FE
DN_MODE 104E
END_ONE 10DE
END_TWO 10EE
FINISH 1186
LF A
LONG 1166
MODE_P 101A
PRNT_A 118C
PRNT_AI 118E
PRNT_CL 1191
PRNT_D 118A
PRNT_DC 1196
PRNT_DT 119A
PRNT_ER 119F
PRNT_HX 119D
PRNT_IN 1193
REG_P 10BA
START 1000
UNSUPP_MODE 1176
WORD 1156