Support ranged memory access

[PhilippvK]

Currently ETISS Writer used old and incorrect syntax for implementing store instructions by infering the width of the mem write from the RHS of the assignment.

        SW {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100011;
            assembly:"{name(rs2)}, {imm}({name(rs1)})";
            behavior: {
                unsigned<XLEN> store_address = X[rs1 % RFS] + (signed)imm;
                MEM[store_address] = (signed<32>)X[rs2 % RFS];
            }
        }

As proposed in Minres/CoreDSL#52 and documented in https://github.com/Minres/CoreDSL/wiki/Expressions#range-operator the recommented syntax is as follows:

        SW {
            encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100011;
            assembly: "{name(rs2)}, {imm}({name(rs1)})";
            behavior: if(rs2 >= RFS || rs1 >= RFS) raise(0, RV_CAUSE_ILLEGAL_INSTRUCTION); else {
                unsigned<XLEN> store_address = (unsigned<XLEN>)(X[rs1] + (signed)imm);
                MEM[store_address+3:store_address] = (unsigned<32>)X[rs2];
            }
        }

The ETISS backend currently ignores this and needs to be fixed before moving to the latest upstream CoreDSL files.

[PhilippvK]

@jokap11 Feel free to have a look

[jokap11]

#82
Can be closed!