diff --git a/m2isar/backends/coverage/coverage_dbg.py b/m2isar/backends/coverage/coverage_dbg.py index f6755cf1..0e1798ec 100644 --- a/m2isar/backends/coverage/coverage_dbg.py +++ b/m2isar/backends/coverage/coverage_dbg.py @@ -60,7 +60,7 @@ def main(): if model_obj.model_version != M2_METAMODEL_VERSION: logger.warning("Loaded model version mismatch") - for core_name, core_obj in model_obj.models.items(): + for core_name, core_obj in model_obj.cores.items(): process_functions(core_obj) process_instructions(core_obj) process_attributes(core_obj) @@ -70,7 +70,7 @@ def main(): ctx = IdMatcherContext() - for core_name, core_obj in model_obj.models.items(): + for core_name, core_obj in model_obj.cores.items(): ctx.arch_name = core_name for fn_name, fn_obj in core_obj.functions.items(): diff --git a/m2isar/backends/coverage/coverage_lcov.py b/m2isar/backends/coverage/coverage_lcov.py index aba52c19..a13d3b4a 100644 --- a/m2isar/backends/coverage/coverage_lcov.py +++ b/m2isar/backends/coverage/coverage_lcov.py @@ -125,12 +125,12 @@ def main(): logger.warning("Loaded model version mismatch") if args.target_arch is not None: - models_to_use = {arch_name: model_obj.models[arch_name] for arch_name in args.target_arch} - model_obj.models = models_to_use + cores_to_use = {arch_name: model_obj.cores[arch_name] for arch_name in args.target_arch} + model_obj.cores = cores_to_use logger.info("preprocessing models") - for core_name, core_obj in model_obj.models.items(): + for core_name, core_obj in model_obj.cores.items(): process_functions(core_obj) process_instructions(core_obj) process_attributes(core_obj) @@ -141,7 +141,7 @@ def main(): ctx = IdMatcherContext() - for core_name, core_obj in model_obj.models.items(): + for core_name, core_obj in model_obj.cores.items(): ctx.arch_name = core_name for fn_name, fn_obj in core_obj.functions.items(): diff --git a/m2isar/backends/disass/disass.py b/m2isar/backends/disass/disass.py index 1193c296..8c71168c 100644 --- a/m2isar/backends/disass/disass.py +++ b/m2isar/backends/disass/disass.py @@ -98,9 +98,9 @@ def main(): if model_obj.model_version != M2_METAMODEL_VERSION: logger.warning("Loaded model version mismatch") - models = model_obj.models + cores = model_obj.cores - core = models[args.core_name] + core = cores[args.core_name] readlen = max(core.instr_classes) // 8 steplen = min(core.instr_classes) // 8 diff --git a/m2isar/backends/etiss/writer.py b/m2isar/backends/etiss/writer.py index c24cd0c6..bd1b41ff 100755 --- a/m2isar/backends/etiss/writer.py +++ b/m2isar/backends/etiss/writer.py @@ -121,18 +121,18 @@ def setup(): start_time = time.strftime("%a, %d %b %Y %H:%M:%S %z", time.localtime()) - assert len(model_obj.models) > 0, "No cores found in metamodel" + assert len(model_obj.cores) > 0, "No cores found in metamodel" - return (model_obj.models, logger, output_base_path, spec_name, start_time, args) + return (model_obj.cores, logger, output_base_path, spec_name, start_time, args) def main(): """etiss_writer main entrypoint function.""" # setup etiss writer - models, logger, output_base_path, spec_name, start_time, args = setup() + cores, logger, output_base_path, spec_name, start_time, args = setup() # preprocess all models - for core_name, core in models.items(): + for core_name, core in cores.items(): logger.info("preprocessing model %s", core_name) process_functions(core) process_instructions(core) @@ -151,7 +151,7 @@ def main(): core.functions = renamed_fns # generate each core in the model - for core_name, core in models.items(): + for core_name, core in cores.items(): logger.info("processing model %s", core_name) # create output files path diff --git a/m2isar/backends/viewer/viewer.py b/m2isar/backends/viewer/viewer.py index c5150caa..4178d3c8 100644 --- a/m2isar/backends/viewer/viewer.py +++ b/m2isar/backends/viewer/viewer.py @@ -73,10 +73,10 @@ def main(): if model_obj.model_version != M2_METAMODEL_VERSION: logger.warning("Loaded model version mismatch") - models = model_obj.models + cores = model_obj.cores # preprocess model - for core_name, core in models.items(): + for core_name, core in cores.items(): logger.info("preprocessing model %s", core_name) process_functions(core) process_instructions(core) @@ -101,7 +101,7 @@ def main(): tree.heading(1, text="Value") # add each core to the treeview - for core_name, core_def in sorted(models.items()): + for core_name, core_def in sorted(cores.items()): core_id = tree.insert("", tk.END, text=core_name) # add constants to tree diff --git a/m2isar/frontends/coredsl2/CoreDSL2.g4 b/m2isar/frontends/coredsl2/CoreDSL2.g4 index 81ff1a73..21e9d672 100644 --- a/m2isar/frontends/coredsl2/CoreDSL2.g4 +++ b/m2isar/frontends/coredsl2/CoreDSL2.g4 @@ -25,7 +25,7 @@ isa section : type_='architectural_state' '{' (declarations+=declaration | expressions+=expression ';')+ '}' # section_arch_state - | type_='functions' '{' functions+=function_definition+ '}' # section_functions + | type_='functions' '{' functions+=function_definition* '}' # section_functions | type_='instructions' attributes+=attribute* '{' instructions+=instruction* '}' # section_instructions | type_='always' attributes+=attribute* '{' always_blocks+=always_block+ '}' # section_always ; diff --git a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Listener.py b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Listener.py index ce53f1f5..f8a03bdd 100644 --- a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Listener.py +++ b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Listener.py @@ -719,6 +719,15 @@ def exitCharacter_constant(self, ctx:CoreDSL2Parser.Character_constantContext): pass + # Enter a parse tree produced by CoreDSL2Parser#string_constant. + def enterString_constant(self, ctx:CoreDSL2Parser.String_constantContext): + pass + + # Exit a parse tree produced by CoreDSL2Parser#string_constant. + def exitString_constant(self, ctx:CoreDSL2Parser.String_constantContext): + pass + + # Enter a parse tree produced by CoreDSL2Parser#double_left_bracket. def enterDouble_left_bracket(self, ctx:CoreDSL2Parser.Double_left_bracketContext): pass diff --git a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Parser.py b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Parser.py index 2839cb3f..2629356f 100644 --- a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Parser.py +++ b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Parser.py @@ -10,306 +10,307 @@ def serializedATN(): return [ - 4,1,102,792,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6, + 4,1,102,797,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6, 7,6,2,7,7,7,2,8,7,8,2,9,7,9,2,10,7,10,2,11,7,11,2,12,7,12,2,13,7, 13,2,14,7,14,2,15,7,15,2,16,7,16,2,17,7,17,2,18,7,18,2,19,7,19,2, 20,7,20,2,21,7,21,2,22,7,22,2,23,7,23,2,24,7,24,2,25,7,25,2,26,7, 26,2,27,7,27,2,28,7,28,2,29,7,29,2,30,7,30,2,31,7,31,2,32,7,32,2, 33,7,33,2,34,7,34,2,35,7,35,2,36,7,36,2,37,7,37,2,38,7,38,2,39,7, 39,2,40,7,40,2,41,7,41,2,42,7,42,2,43,7,43,2,44,7,44,2,45,7,45,2, - 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1,3,1,3,1,3,1,3,5,3,172,8,3,10,3,12,3,175,9,3,1,3,1,3,1,3,5,3,180, + 8,3,10,3,12,3,183,9,3,1,3,1,3,5,3,187,8,3,10,3,12,3,190,9,3,1,3, + 1,3,1,3,5,3,195,8,3,10,3,12,3,198,9,3,1,3,1,3,4,3,202,8,3,11,3,12, + 3,203,1,3,1,3,3,3,208,8,3,1,4,1,4,5,4,212,8,4,10,4,12,4,215,9,4, + 1,4,1,4,1,5,1,5,5,5,221,8,5,10,5,12,5,224,9,5,1,5,1,5,1,5,1,5,1, + 5,1,5,5,5,232,8,5,10,5,12,5,235,9,5,1,5,1,5,1,5,1,5,1,5,1,5,1,5, + 1,5,1,5,3,5,246,8,5,1,5,3,5,249,8,5,1,5,1,5,1,5,1,5,1,5,1,6,1,6, + 1,6,5,6,259,8,6,10,6,12,6,262,9,6,1,7,1,7,1,7,1,7,1,7,1,7,1,7,1, + 7,3,7,272,8,7,1,8,1,8,1,8,1,8,1,8,3,8,279,8,8,1,8,1,8,5,8,283,8, + 8,10,8,12,8,286,9,8,1,8,1,8,1,8,1,8,1,8,1,8,3,8,294,8,8,1,8,1,8, + 5,8,298,8,8,10,8,12,8,301,9,8,1,8,1,8,3,8,305,8,8,3,8,307,8,8,1, + 9,1,9,1,9,5,9,312,8,9,10,9,12,9,315,9,9,1,10,1,10,3,10,319,8,10, + 1,11,1,11,1,11,1,11,1,11,1,11,5,11,327,8,11,10,11,12,11,330,9,11, + 3,11,332,8,11,1,11,1,11,1,11,1,11,1,11,1,11,1,11,1,11,1,11,1,11, + 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1,0,0,0,92,787,1,0,0,0,94,789,1,0,0,0,96,98,3,2,1,0,97,96,1,0,0, - 0,98,101,1,0,0,0,99,97,1,0,0,0,99,100,1,0,0,0,100,103,1,0,0,0,101, - 99,1,0,0,0,102,104,3,4,2,0,103,102,1,0,0,0,104,105,1,0,0,0,105,103, - 1,0,0,0,105,106,1,0,0,0,106,1,1,0,0,0,107,108,5,1,0,0,108,109,5, - 99,0,0,109,3,1,0,0,0,110,111,5,2,0,0,111,121,5,96,0,0,112,113,5, - 3,0,0,113,118,5,96,0,0,114,115,5,4,0,0,115,117,5,96,0,0,116,114, - 1,0,0,0,117,120,1,0,0,0,118,116,1,0,0,0,118,119,1,0,0,0,119,122, - 1,0,0,0,120,118,1,0,0,0,121,112,1,0,0,0,121,122,1,0,0,0,122,123, - 1,0,0,0,123,127,5,5,0,0,124,126,3,6,3,0,125,124,1,0,0,0,126,129, - 1,0,0,0,127,125,1,0,0,0,127,128,1,0,0,0,128,130,1,0,0,0,129,127, - 1,0,0,0,130,153,5,6,0,0,131,132,5,7,0,0,132,142,5,96,0,0,133,134, - 5,8,0,0,134,139,5,96,0,0,135,136,5,4,0,0,136,138,5,96,0,0,137,135, - 1,0,0,0,138,141,1,0,0,0,139,137,1,0,0,0,139,140,1,0,0,0,140,143, - 1,0,0,0,141,139,1,0,0,0,142,133,1,0,0,0,142,143,1,0,0,0,143,144, - 1,0,0,0,144,148,5,5,0,0,145,147,3,6,3,0,146,145,1,0,0,0,147,150, - 1,0,0,0,148,146,1,0,0,0,148,149,1,0,0,0,149,151,1,0,0,0,150,148, - 1,0,0,0,151,153,5,6,0,0,152,110,1,0,0,0,152,131,1,0,0,0,153,5,1, - 0,0,0,154,155,5,9,0,0,155,160,5,5,0,0,156,161,3,34,17,0,157,158, - 3,68,34,0,158,159,5,10,0,0,159,161,1,0,0,0,160,156,1,0,0,0,160,157, - 1,0,0,0,161,162,1,0,0,0,162,160,1,0,0,0,162,163,1,0,0,0,163,164, - 1,0,0,0,164,165,5,6,0,0,165,206,1,0,0,0,166,167,5,11,0,0,167,169, - 5,5,0,0,168,170,3,16,8,0,169,168,1,0,0,0,170,171,1,0,0,0,171,169, - 1,0,0,0,171,172,1,0,0,0,172,173,1,0,0,0,173,174,5,6,0,0,174,206, - 1,0,0,0,175,179,5,12,0,0,176,178,3,46,23,0,177,176,1,0,0,0,178,181, - 1,0,0,0,179,177,1,0,0,0,179,180,1,0,0,0,180,182,1,0,0,0,181,179, - 1,0,0,0,182,186,5,5,0,0,183,185,3,10,5,0,184,183,1,0,0,0,185,188, - 1,0,0,0,186,184,1,0,0,0,186,187,1,0,0,0,187,189,1,0,0,0,188,186, - 1,0,0,0,189,206,5,6,0,0,190,194,5,13,0,0,191,193,3,46,23,0,192,191, - 1,0,0,0,193,196,1,0,0,0,194,192,1,0,0,0,194,195,1,0,0,0,195,197, - 1,0,0,0,196,194,1,0,0,0,197,199,5,5,0,0,198,200,3,8,4,0,199,198, - 1,0,0,0,200,201,1,0,0,0,201,199,1,0,0,0,201,202,1,0,0,0,202,203, - 1,0,0,0,203,204,5,6,0,0,204,206,1,0,0,0,205,154,1,0,0,0,205,166, - 1,0,0,0,205,175,1,0,0,0,205,190,1,0,0,0,206,7,1,0,0,0,207,211,5, - 96,0,0,208,210,3,46,23,0,209,208,1,0,0,0,210,213,1,0,0,0,211,209, - 1,0,0,0,211,212,1,0,0,0,212,214,1,0,0,0,213,211,1,0,0,0,214,215, - 3,28,14,0,215,9,1,0,0,0,216,220,5,96,0,0,217,219,3,46,23,0,218,217, - 1,0,0,0,219,222,1,0,0,0,220,218,1,0,0,0,220,221,1,0,0,0,221,223, - 1,0,0,0,222,220,1,0,0,0,223,224,5,5,0,0,224,225,5,14,0,0,225,226, - 5,15,0,0,226,231,3,14,7,0,227,228,5,16,0,0,228,230,3,14,7,0,229, - 227,1,0,0,0,230,233,1,0,0,0,231,229,1,0,0,0,231,232,1,0,0,0,232, - 234,1,0,0,0,233,231,1,0,0,0,234,246,5,10,0,0,235,236,5,17,0,0,236, - 243,5,15,0,0,237,244,5,99,0,0,238,239,5,5,0,0,239,240,5,99,0,0,240, - 241,5,4,0,0,241,242,5,99,0,0,242,244,5,6,0,0,243,237,1,0,0,0,243, - 238,1,0,0,0,244,245,1,0,0,0,245,247,5,10,0,0,246,235,1,0,0,0,246, - 247,1,0,0,0,247,248,1,0,0,0,248,249,5,18,0,0,249,250,5,15,0,0,250, - 251,3,22,11,0,251,252,5,6,0,0,252,11,1,0,0,0,253,258,3,14,7,0,254, - 255,5,16,0,0,255,257,3,14,7,0,256,254,1,0,0,0,257,260,1,0,0,0,258, - 256,1,0,0,0,258,259,1,0,0,0,259,13,1,0,0,0,260,258,1,0,0,0,261,270, - 3,76,38,0,262,263,5,96,0,0,263,264,5,91,0,0,264,265,3,76,38,0,265, - 266,5,15,0,0,266,267,3,76,38,0,267,268,5,92,0,0,268,270,1,0,0,0, - 269,261,1,0,0,0,269,262,1,0,0,0,270,15,1,0,0,0,271,272,5,19,0,0, - 272,273,3,36,18,0,273,274,5,96,0,0,274,276,5,20,0,0,275,277,3,18, - 9,0,276,275,1,0,0,0,276,277,1,0,0,0,277,278,1,0,0,0,278,282,5,21, - 0,0,279,281,3,46,23,0,280,279,1,0,0,0,281,284,1,0,0,0,282,280,1, - 0,0,0,282,283,1,0,0,0,283,285,1,0,0,0,284,282,1,0,0,0,285,286,5, - 10,0,0,286,305,1,0,0,0,287,288,3,36,18,0,288,289,5,96,0,0,289,291, - 5,20,0,0,290,292,3,18,9,0,291,290,1,0,0,0,291,292,1,0,0,0,292,293, - 1,0,0,0,293,297,5,21,0,0,294,296,3,46,23,0,295,294,1,0,0,0,296,299, - 1,0,0,0,297,295,1,0,0,0,297,298,1,0,0,0,298,302,1,0,0,0,299,297, - 1,0,0,0,300,303,3,28,14,0,301,303,5,10,0,0,302,300,1,0,0,0,302,301, - 1,0,0,0,303,305,1,0,0,0,304,271,1,0,0,0,304,287,1,0,0,0,305,17,1, - 0,0,0,306,311,3,20,10,0,307,308,5,4,0,0,308,310,3,20,10,0,309,307, - 1,0,0,0,310,313,1,0,0,0,311,309,1,0,0,0,311,312,1,0,0,0,312,19,1, - 0,0,0,313,311,1,0,0,0,314,316,3,36,18,0,315,317,3,58,29,0,316,315, - 1,0,0,0,316,317,1,0,0,0,317,21,1,0,0,0,318,408,3,28,14,0,319,320, - 5,96,0,0,320,329,5,20,0,0,321,326,3,68,34,0,322,323,5,4,0,0,323, - 325,3,68,34,0,324,322,1,0,0,0,325,328,1,0,0,0,326,324,1,0,0,0,326, - 327,1,0,0,0,327,330,1,0,0,0,328,326,1,0,0,0,329,321,1,0,0,0,329, - 330,1,0,0,0,330,331,1,0,0,0,331,332,5,21,0,0,332,408,5,10,0,0,333, - 334,5,22,0,0,334,335,5,20,0,0,335,336,3,68,34,0,336,337,5,21,0,0, - 337,347,3,22,11,0,338,339,5,23,0,0,339,340,5,22,0,0,340,341,5,20, - 0,0,341,342,3,68,34,0,342,343,5,21,0,0,343,344,3,22,11,0,344,346, - 1,0,0,0,345,338,1,0,0,0,346,349,1,0,0,0,347,345,1,0,0,0,347,348, - 1,0,0,0,348,352,1,0,0,0,349,347,1,0,0,0,350,351,5,23,0,0,351,353, - 3,22,11,0,352,350,1,0,0,0,352,353,1,0,0,0,353,408,1,0,0,0,354,355, - 5,24,0,0,355,356,5,20,0,0,356,357,3,32,16,0,357,358,5,21,0,0,358, - 359,3,22,11,0,359,408,1,0,0,0,360,361,5,25,0,0,361,362,5,20,0,0, - 362,363,3,68,34,0,363,364,5,21,0,0,364,365,3,22,11,0,365,408,1,0, - 0,0,366,367,5,26,0,0,367,368,3,22,11,0,368,369,5,25,0,0,369,370, - 5,20,0,0,370,371,3,68,34,0,371,372,5,21,0,0,372,373,5,10,0,0,373, - 408,1,0,0,0,374,375,5,27,0,0,375,376,5,20,0,0,376,377,3,68,34,0, - 377,378,5,21,0,0,378,382,5,5,0,0,379,381,3,24,12,0,380,379,1,0,0, - 0,381,384,1,0,0,0,382,380,1,0,0,0,382,383,1,0,0,0,383,388,1,0,0, - 0,384,382,1,0,0,0,385,387,3,26,13,0,386,385,1,0,0,0,387,390,1,0, - 0,0,388,386,1,0,0,0,388,389,1,0,0,0,389,391,1,0,0,0,390,388,1,0, - 0,0,391,392,5,6,0,0,392,408,1,0,0,0,393,395,5,28,0,0,394,396,3,68, - 34,0,395,394,1,0,0,0,395,396,1,0,0,0,396,397,1,0,0,0,397,408,5,10, - 0,0,398,399,5,29,0,0,399,408,5,10,0,0,400,401,5,30,0,0,401,408,5, - 10,0,0,402,403,5,31,0,0,403,408,3,22,11,0,404,405,3,68,34,0,405, - 406,5,10,0,0,406,408,1,0,0,0,407,318,1,0,0,0,407,319,1,0,0,0,407, - 333,1,0,0,0,407,354,1,0,0,0,407,360,1,0,0,0,407,366,1,0,0,0,407, - 374,1,0,0,0,407,393,1,0,0,0,407,398,1,0,0,0,407,400,1,0,0,0,407, - 402,1,0,0,0,407,404,1,0,0,0,408,23,1,0,0,0,409,411,3,26,13,0,410, - 409,1,0,0,0,411,412,1,0,0,0,412,410,1,0,0,0,412,413,1,0,0,0,413, - 415,1,0,0,0,414,416,3,22,11,0,415,414,1,0,0,0,416,417,1,0,0,0,417, - 415,1,0,0,0,417,418,1,0,0,0,418,25,1,0,0,0,419,420,5,32,0,0,420, - 421,3,68,34,0,421,422,5,15,0,0,422,426,1,0,0,0,423,424,5,33,0,0, - 424,426,5,15,0,0,425,419,1,0,0,0,425,423,1,0,0,0,426,27,1,0,0,0, - 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540,1,0,0,0,553,542,1,0,0,0,553,554,1,0,0,0,554,555,1,0,0,0,555, + 556,5,51,0,0,556,47,1,0,0,0,557,558,5,36,0,0,558,566,3,70,35,0,559, + 560,5,4,0,0,560,561,3,70,35,0,561,562,5,4,0,0,562,563,3,70,35,0, + 563,564,5,4,0,0,564,565,3,70,35,0,565,567,1,0,0,0,566,559,1,0,0, + 0,566,567,1,0,0,0,567,568,1,0,0,0,568,569,5,37,0,0,569,49,1,0,0, + 0,570,575,3,52,26,0,571,572,5,4,0,0,572,574,3,52,26,0,573,571,1, + 0,0,0,574,577,1,0,0,0,575,573,1,0,0,0,575,576,1,0,0,0,576,51,1,0, + 0,0,577,575,1,0,0,0,578,583,5,96,0,0,579,580,5,96,0,0,580,581,5, + 50,0,0,581,583,3,68,34,0,582,578,1,0,0,0,582,579,1,0,0,0,583,53, + 1,0,0,0,584,585,3,56,28,0,585,590,3,58,29,0,586,587,5,4,0,0,587, + 589,3,58,29,0,588,586,1,0,0,0,589,592,1,0,0,0,590,588,1,0,0,0,590, + 591,1,0,0,0,591,593,1,0,0,0,592,590,1,0,0,0,593,594,5,10,0,0,594, + 55,1,0,0,0,595,598,3,36,18,0,596,598,3,92,46,0,597,595,1,0,0,0,597, + 596,1,0,0,0,598,57,1,0,0,0,599,606,5,96,0,0,600,601,5,91,0,0,601, + 602,3,68,34,0,602,603,5,92,0,0,603,605,1,0,0,0,604,600,1,0,0,0,605, + 608,1,0,0,0,606,604,1,0,0,0,606,607,1,0,0,0,607,612,1,0,0,0,608, + 606,1,0,0,0,609,611,3,46,23,0,610,609,1,0,0,0,611,614,1,0,0,0,612, + 610,1,0,0,0,612,613,1,0,0,0,613,617,1,0,0,0,614,612,1,0,0,0,615, + 616,5,50,0,0,616,618,3,60,30,0,617,615,1,0,0,0,617,618,1,0,0,0,618, + 59,1,0,0,0,619,628,3,68,34,0,620,621,5,5,0,0,621,623,3,62,31,0,622, + 624,5,4,0,0,623,622,1,0,0,0,623,624,1,0,0,0,624,625,1,0,0,0,625, + 626,5,6,0,0,626,628,1,0,0,0,627,619,1,0,0,0,627,620,1,0,0,0,628, + 61,1,0,0,0,629,632,3,64,32,0,630,632,3,60,30,0,631,629,1,0,0,0,631, + 630,1,0,0,0,632,640,1,0,0,0,633,636,5,4,0,0,634,637,3,64,32,0,635, + 637,3,60,30,0,636,634,1,0,0,0,636,635,1,0,0,0,637,639,1,0,0,0,638, + 633,1,0,0,0,639,642,1,0,0,0,640,638,1,0,0,0,640,641,1,0,0,0,641, + 63,1,0,0,0,642,640,1,0,0,0,643,645,3,66,33,0,644,643,1,0,0,0,645, + 646,1,0,0,0,646,644,1,0,0,0,646,647,1,0,0,0,647,648,1,0,0,0,648, + 649,5,50,0,0,649,650,3,60,30,0,650,65,1,0,0,0,651,652,5,91,0,0,652, + 653,3,68,34,0,653,654,5,92,0,0,654,658,1,0,0,0,655,656,5,52,0,0, + 656,658,5,96,0,0,657,651,1,0,0,0,657,655,1,0,0,0,658,67,1,0,0,0, + 659,660,6,34,-1,0,660,691,3,70,35,0,661,662,7,3,0,0,662,691,5,96, + 0,0,663,664,5,96,0,0,664,673,5,20,0,0,665,670,3,68,34,0,666,667, + 5,4,0,0,667,669,3,68,34,0,668,666,1,0,0,0,669,672,1,0,0,0,670,668, + 1,0,0,0,670,671,1,0,0,0,671,674,1,0,0,0,672,670,1,0,0,0,673,665, + 1,0,0,0,673,674,1,0,0,0,674,675,1,0,0,0,675,691,5,21,0,0,676,677, + 7,4,0,0,677,691,3,68,34,17,678,679,7,5,0,0,679,691,3,68,34,16,680, + 681,7,6,0,0,681,691,3,68,34,15,682,685,5,20,0,0,683,686,3,36,18, + 0,684,686,3,40,20,0,685,683,1,0,0,0,685,684,1,0,0,0,686,687,1,0, + 0,0,687,688,5,21,0,0,688,689,3,68,34,14,689,691,1,0,0,0,690,659, + 1,0,0,0,690,661,1,0,0,0,690,663,1,0,0,0,690,676,1,0,0,0,690,678, + 1,0,0,0,690,680,1,0,0,0,690,682,1,0,0,0,691,747,1,0,0,0,692,693, + 10,13,0,0,693,694,7,7,0,0,694,746,3,68,34,14,695,696,10,12,0,0,696, + 697,7,8,0,0,697,746,3,68,34,13,698,699,10,11,0,0,699,700,7,9,0,0, + 700,746,3,68,34,12,701,702,10,10,0,0,702,703,7,10,0,0,703,746,3, + 68,34,11,704,705,10,9,0,0,705,706,7,11,0,0,706,746,3,68,34,10,707, + 708,10,8,0,0,708,709,5,35,0,0,709,746,3,68,34,9,710,711,10,7,0,0, + 711,712,5,68,0,0,712,746,3,68,34,8,713,714,10,6,0,0,714,715,5,69, + 0,0,715,746,3,68,34,7,716,717,10,5,0,0,717,718,5,70,0,0,718,746, + 3,68,34,6,719,720,10,4,0,0,720,721,5,71,0,0,721,746,3,68,34,5,722, + 723,10,3,0,0,723,724,5,16,0,0,724,746,3,68,34,4,725,726,10,2,0,0, + 726,727,5,72,0,0,727,728,3,68,34,0,728,729,5,15,0,0,729,730,3,68, + 34,2,730,746,1,0,0,0,731,732,10,1,0,0,732,733,7,12,0,0,733,746,3, + 68,34,1,734,735,10,20,0,0,735,736,5,91,0,0,736,739,3,68,34,0,737, + 738,5,15,0,0,738,740,3,68,34,0,739,737,1,0,0,0,739,740,1,0,0,0,740, + 741,1,0,0,0,741,742,5,92,0,0,742,746,1,0,0,0,743,744,10,18,0,0,744, + 746,7,4,0,0,745,692,1,0,0,0,745,695,1,0,0,0,745,698,1,0,0,0,745, + 701,1,0,0,0,745,704,1,0,0,0,745,707,1,0,0,0,745,710,1,0,0,0,745, + 713,1,0,0,0,745,716,1,0,0,0,745,719,1,0,0,0,745,722,1,0,0,0,745, + 725,1,0,0,0,745,731,1,0,0,0,745,734,1,0,0,0,745,743,1,0,0,0,746, + 749,1,0,0,0,747,745,1,0,0,0,747,748,1,0,0,0,748,69,1,0,0,0,749,747, + 1,0,0,0,750,762,5,96,0,0,751,762,3,74,37,0,752,754,3,72,36,0,753, + 752,1,0,0,0,754,755,1,0,0,0,755,753,1,0,0,0,755,756,1,0,0,0,756, + 762,1,0,0,0,757,758,5,20,0,0,758,759,3,68,34,0,759,760,5,21,0,0, + 760,762,1,0,0,0,761,750,1,0,0,0,761,751,1,0,0,0,761,753,1,0,0,0, + 761,757,1,0,0,0,762,71,1,0,0,0,763,764,7,13,0,0,764,73,1,0,0,0,765, + 771,3,76,38,0,766,771,3,78,39,0,767,771,3,82,41,0,768,771,3,84,42, + 0,769,771,3,80,40,0,770,765,1,0,0,0,770,766,1,0,0,0,770,767,1,0, + 0,0,770,768,1,0,0,0,770,769,1,0,0,0,771,75,1,0,0,0,772,773,5,95, + 0,0,773,77,1,0,0,0,774,775,5,94,0,0,775,79,1,0,0,0,776,777,5,93, + 0,0,777,81,1,0,0,0,778,779,5,97,0,0,779,83,1,0,0,0,780,781,5,99, + 0,0,781,85,1,0,0,0,782,783,5,91,0,0,783,784,5,91,0,0,784,87,1,0, + 0,0,785,786,5,92,0,0,786,787,5,92,0,0,787,89,1,0,0,0,788,789,7,14, + 0,0,789,91,1,0,0,0,790,791,7,15,0,0,791,93,1,0,0,0,792,793,7,16, + 0,0,793,95,1,0,0,0,794,795,7,17,0,0,795,97,1,0,0,0,88,101,107,120, + 123,129,141,144,150,154,162,164,173,181,188,196,203,207,213,222, + 233,245,248,260,271,278,284,293,299,304,306,313,318,328,331,349, + 354,384,390,397,409,414,419,427,433,440,444,447,450,458,461,466, + 468,477,480,487,495,503,509,519,524,530,548,553,566,575,582,590, + 597,606,612,617,623,627,631,636,640,646,657,670,673,685,690,739, + 745,747,755,761,770 ] class CoreDSL2Parser ( Parser ): @@ -409,12 +410,13 @@ class CoreDSL2Parser ( Parser ): RULE_floating_constant = 39 RULE_bool_constant = 40 RULE_character_constant = 41 - RULE_double_left_bracket = 42 - RULE_double_right_bracket = 43 - RULE_data_types = 44 - RULE_type_qualifier = 45 - RULE_storage_class_specifier = 46 - RULE_struct_or_union = 47 + RULE_string_constant = 42 + RULE_double_left_bracket = 43 + RULE_double_right_bracket = 44 + RULE_data_types = 45 + RULE_type_qualifier = 46 + RULE_storage_class_specifier = 47 + RULE_struct_or_union = 48 ruleNames = [ "description_content", "import_file", "isa", "section", "always_block", "instruction", "rule_encoding", "encoding_entry", @@ -428,9 +430,9 @@ class CoreDSL2Parser ( Parser ): "declarator", "initializer", "initializerList", "designated_initializer", "designator", "expression", "primary", "string_literal", "constant", "integer_constant", "floating_constant", - "bool_constant", "character_constant", "double_left_bracket", - "double_right_bracket", "data_types", "type_qualifier", - "storage_class_specifier", "struct_or_union" ] + "bool_constant", "character_constant", "string_constant", + "double_left_bracket", "double_right_bracket", "data_types", + "type_qualifier", "storage_class_specifier", "struct_or_union" ] EOF = Token.EOF T__0=1 @@ -597,25 +599,25 @@ def description_content(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 99 + self.state = 101 self._errHandler.sync(self) _la = self._input.LA(1) while _la==1: - self.state = 96 + self.state = 98 localctx._import_file = self.import_file() localctx.imports.append(localctx._import_file) - self.state = 101 + self.state = 103 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 103 + self.state = 105 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 102 + self.state = 104 localctx._isa = self.isa() localctx.definitions.append(localctx._isa) - self.state = 105 + self.state = 107 self._errHandler.sync(self) _la = self._input.LA(1) if not (_la==2 or _la==7): @@ -667,9 +669,9 @@ def import_file(self): self.enterRule(localctx, 2, self.RULE_import_file) try: self.enterOuterAlt(localctx, 1) - self.state = 107 + self.state = 109 self.match(CoreDSL2Parser.T__0) - self.state = 108 + self.state = 110 localctx.uri = self.match(CoreDSL2Parser.STRING) except RecognitionException as re: localctx.exception = re @@ -780,101 +782,101 @@ def isa(self): self.enterRule(localctx, 4, self.RULE_isa) self._la = 0 # Token type try: - self.state = 152 + self.state = 154 self._errHandler.sync(self) token = self._input.LA(1) if token in [2]: localctx = CoreDSL2Parser.Instruction_setContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 110 + self.state = 112 self.match(CoreDSL2Parser.T__1) - self.state = 111 + self.state = 113 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 121 + self.state = 123 self._errHandler.sync(self) _la = self._input.LA(1) if _la==3: - self.state = 112 + self.state = 114 self.match(CoreDSL2Parser.T__2) - self.state = 113 + self.state = 115 localctx._IDENTIFIER = self.match(CoreDSL2Parser.IDENTIFIER) localctx.extension.append(localctx._IDENTIFIER) - self.state = 118 + self.state = 120 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 114 + self.state = 116 self.match(CoreDSL2Parser.T__3) - self.state = 115 + self.state = 117 localctx._IDENTIFIER = self.match(CoreDSL2Parser.IDENTIFIER) localctx.extension.append(localctx._IDENTIFIER) - self.state = 120 + self.state = 122 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 123 + self.state = 125 self.match(CoreDSL2Parser.T__4) - self.state = 127 + self.state = 129 self._errHandler.sync(self) _la = self._input.LA(1) while (((_la) & ~0x3f) == 0 and ((1 << _la) & 14848) != 0): - self.state = 124 + self.state = 126 localctx._section = self.section() localctx.sections.append(localctx._section) - self.state = 129 + self.state = 131 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 130 + self.state = 132 self.match(CoreDSL2Parser.T__5) pass elif token in [7]: localctx = CoreDSL2Parser.Core_defContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 131 + self.state = 133 self.match(CoreDSL2Parser.T__6) - self.state = 132 + self.state = 134 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 142 + self.state = 144 self._errHandler.sync(self) _la = self._input.LA(1) if _la==8: - self.state = 133 + self.state = 135 self.match(CoreDSL2Parser.T__7) - self.state = 134 + self.state = 136 localctx._IDENTIFIER = self.match(CoreDSL2Parser.IDENTIFIER) localctx.contributing_types.append(localctx._IDENTIFIER) - self.state = 139 + self.state = 141 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 135 + self.state = 137 self.match(CoreDSL2Parser.T__3) - self.state = 136 + self.state = 138 localctx._IDENTIFIER = self.match(CoreDSL2Parser.IDENTIFIER) localctx.contributing_types.append(localctx._IDENTIFIER) - self.state = 141 + self.state = 143 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 144 + self.state = 146 self.match(CoreDSL2Parser.T__4) - self.state = 148 + self.state = 150 self._errHandler.sync(self) _la = self._input.LA(1) while (((_la) & ~0x3f) == 0 and ((1 << _la) & 14848) != 0): - self.state = 145 + self.state = 147 localctx._section = self.section() localctx.sections.append(localctx._section) - self.state = 150 + self.state = 152 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 151 + self.state = 153 self.match(CoreDSL2Parser.T__5) pass else: @@ -1061,134 +1063,132 @@ def section(self): self.enterRule(localctx, 6, self.RULE_section) self._la = 0 # Token type try: - self.state = 205 + self.state = 207 self._errHandler.sync(self) token = self._input.LA(1) if token in [9]: localctx = CoreDSL2Parser.Section_arch_stateContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 154 + self.state = 156 localctx.type_ = self.match(CoreDSL2Parser.T__8) - self.state = 155 + self.state = 157 self.match(CoreDSL2Parser.T__4) - self.state = 160 + self.state = 162 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 160 + self.state = 162 self._errHandler.sync(self) token = self._input.LA(1) if token in [19, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 85, 86, 87, 88, 89, 90]: - self.state = 156 + self.state = 158 localctx._declaration = self.declaration() localctx.declarations.append(localctx._declaration) pass elif token in [20, 34, 35, 52, 53, 54, 55, 56, 57, 58, 59, 93, 94, 95, 96, 97, 98, 99]: - self.state = 157 + self.state = 159 localctx._expression = self.expression(0) localctx.expressions.append(localctx._expression) - self.state = 158 + self.state = 160 self.match(CoreDSL2Parser.T__9) pass else: raise NoViableAltException(self) - self.state = 162 + self.state = 164 self._errHandler.sync(self) _la = self._input.LA(1) if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & 1149543581549592576) != 0) or ((((_la - 85)) & ~0x3f) == 0 and ((1 << (_la - 85)) & 32575) != 0)): break - self.state = 164 + self.state = 166 self.match(CoreDSL2Parser.T__5) pass elif token in [11]: localctx = CoreDSL2Parser.Section_functionsContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 166 + self.state = 168 localctx.type_ = self.match(CoreDSL2Parser.T__10) - self.state = 167 + self.state = 169 self.match(CoreDSL2Parser.T__4) - self.state = 169 + self.state = 173 self._errHandler.sync(self) _la = self._input.LA(1) - while True: - self.state = 168 + while (((_la) & ~0x3f) == 0 and ((1 << _la) & 562675076038656) != 0) or _la==89 or _la==90: + self.state = 170 localctx._function_definition = self.function_definition() localctx.functions.append(localctx._function_definition) - self.state = 171 + self.state = 175 self._errHandler.sync(self) _la = self._input.LA(1) - if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & 562675076038656) != 0) or _la==89 or _la==90): - break - self.state = 173 + self.state = 176 self.match(CoreDSL2Parser.T__5) pass elif token in [12]: localctx = CoreDSL2Parser.Section_instructionsContext(self, localctx) self.enterOuterAlt(localctx, 3) - self.state = 175 + self.state = 177 localctx.type_ = self.match(CoreDSL2Parser.T__11) - self.state = 179 + self.state = 181 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 176 + self.state = 178 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 181 + self.state = 183 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 182 + self.state = 184 self.match(CoreDSL2Parser.T__4) - self.state = 186 + self.state = 188 self._errHandler.sync(self) _la = self._input.LA(1) while _la==96: - self.state = 183 + self.state = 185 localctx._instruction = self.instruction() localctx.instructions.append(localctx._instruction) - self.state = 188 + self.state = 190 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 189 + self.state = 191 self.match(CoreDSL2Parser.T__5) pass elif token in [13]: localctx = CoreDSL2Parser.Section_alwaysContext(self, localctx) self.enterOuterAlt(localctx, 4) - self.state = 190 + self.state = 192 localctx.type_ = self.match(CoreDSL2Parser.T__12) - self.state = 194 + self.state = 196 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 191 + self.state = 193 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 196 + self.state = 198 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 197 + self.state = 199 self.match(CoreDSL2Parser.T__4) - self.state = 199 + self.state = 201 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 198 + self.state = 200 localctx._always_block = self.always_block() localctx.always_blocks.append(localctx._always_block) - self.state = 201 + self.state = 203 self._errHandler.sync(self) _la = self._input.LA(1) if not (_la==96): break - self.state = 203 + self.state = 205 self.match(CoreDSL2Parser.T__5) pass else: @@ -1255,20 +1255,20 @@ def always_block(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 207 + self.state = 209 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 211 + self.state = 213 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 208 + self.state = 210 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 213 + self.state = 215 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 214 + self.state = 216 localctx.behavior = self.block() except RecognitionException as re: localctx.exception = re @@ -1348,84 +1348,84 @@ def instruction(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 216 + self.state = 218 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 220 + self.state = 222 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 217 + self.state = 219 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 222 + self.state = 224 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 223 + self.state = 225 self.match(CoreDSL2Parser.T__4) - self.state = 224 + self.state = 226 self.match(CoreDSL2Parser.T__13) - self.state = 225 + self.state = 227 self.match(CoreDSL2Parser.T__14) - self.state = 226 + self.state = 228 localctx._encoding_entry = self.encoding_entry() localctx.encoding.append(localctx._encoding_entry) - self.state = 231 + self.state = 233 self._errHandler.sync(self) _la = self._input.LA(1) while _la==16: - self.state = 227 + self.state = 229 self.match(CoreDSL2Parser.T__15) - self.state = 228 + self.state = 230 localctx._encoding_entry = self.encoding_entry() localctx.encoding.append(localctx._encoding_entry) - self.state = 233 + self.state = 235 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 234 + self.state = 236 self.match(CoreDSL2Parser.T__9) - self.state = 246 + self.state = 248 self._errHandler.sync(self) _la = self._input.LA(1) if _la==17: - self.state = 235 + self.state = 237 self.match(CoreDSL2Parser.T__16) - self.state = 236 + self.state = 238 self.match(CoreDSL2Parser.T__14) - self.state = 243 + self.state = 245 self._errHandler.sync(self) token = self._input.LA(1) if token in [99]: - self.state = 237 + self.state = 239 localctx.assembly = self.match(CoreDSL2Parser.STRING) pass elif token in [5]: - self.state = 238 + self.state = 240 self.match(CoreDSL2Parser.T__4) - self.state = 239 + self.state = 241 localctx.mnemonic = self.match(CoreDSL2Parser.STRING) - self.state = 240 + self.state = 242 self.match(CoreDSL2Parser.T__3) - self.state = 241 + self.state = 243 localctx.assembly = self.match(CoreDSL2Parser.STRING) - self.state = 242 + self.state = 244 self.match(CoreDSL2Parser.T__5) pass else: raise NoViableAltException(self) - self.state = 245 + self.state = 247 self.match(CoreDSL2Parser.T__9) - self.state = 248 + self.state = 250 self.match(CoreDSL2Parser.T__17) - self.state = 249 + self.state = 251 self.match(CoreDSL2Parser.T__14) - self.state = 250 + self.state = 252 localctx.behavior = self.statement() - self.state = 251 + self.state = 253 self.match(CoreDSL2Parser.T__5) except RecognitionException as re: localctx.exception = re @@ -1479,19 +1479,19 @@ def rule_encoding(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 253 + self.state = 255 localctx._encoding_entry = self.encoding_entry() localctx.fields.append(localctx._encoding_entry) - self.state = 258 + self.state = 260 self._errHandler.sync(self) _la = self._input.LA(1) while _la==16: - self.state = 254 + self.state = 256 self.match(CoreDSL2Parser.T__15) - self.state = 255 + self.state = 257 localctx._encoding_entry = self.encoding_entry() localctx.fields.append(localctx._encoding_entry) - self.state = 260 + self.state = 262 self._errHandler.sync(self) _la = self._input.LA(1) @@ -1590,29 +1590,29 @@ def encoding_entry(self): localctx = CoreDSL2Parser.Encoding_entryContext(self, self._ctx, self.state) self.enterRule(localctx, 14, self.RULE_encoding_entry) try: - self.state = 269 + self.state = 271 self._errHandler.sync(self) token = self._input.LA(1) if token in [95]: localctx = CoreDSL2Parser.Bit_valueContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 261 + self.state = 263 localctx.value = self.integer_constant() pass elif token in [96]: localctx = CoreDSL2Parser.Bit_fieldContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 262 + self.state = 264 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 263 + self.state = 265 self.match(CoreDSL2Parser.LEFT_BR) - self.state = 264 + self.state = 266 localctx.left = self.integer_constant() - self.state = 265 + self.state = 267 self.match(CoreDSL2Parser.T__14) - self.state = 266 + self.state = 268 localctx.right = self.integer_constant() - self.state = 267 + self.state = 269 self.match(CoreDSL2Parser.RIGHT_BR) pass else: @@ -1689,81 +1689,81 @@ def function_definition(self): self.enterRule(localctx, 16, self.RULE_function_definition) self._la = 0 # Token type try: - self.state = 304 + self.state = 306 self._errHandler.sync(self) token = self._input.LA(1) if token in [19]: self.enterOuterAlt(localctx, 1) - self.state = 271 + self.state = 273 localctx.extern = self.match(CoreDSL2Parser.T__18) - self.state = 272 + self.state = 274 localctx.type_ = self.type_specifier() - self.state = 273 + self.state = 275 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 274 - self.match(CoreDSL2Parser.T__19) self.state = 276 + self.match(CoreDSL2Parser.T__19) + self.state = 278 self._errHandler.sync(self) _la = self._input.LA(1) if ((((_la - 38)) & ~0x3f) == 0 and ((1 << (_la - 38)) & 6755399441057791) != 0): - self.state = 275 + self.state = 277 localctx.params = self.parameter_list() - self.state = 278 + self.state = 280 self.match(CoreDSL2Parser.T__20) - self.state = 282 + self.state = 284 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 279 + self.state = 281 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 284 + self.state = 286 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 285 + self.state = 287 self.match(CoreDSL2Parser.T__9) pass elif token in [38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 89, 90]: self.enterOuterAlt(localctx, 2) - self.state = 287 + self.state = 289 localctx.type_ = self.type_specifier() - self.state = 288 + self.state = 290 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 289 - self.match(CoreDSL2Parser.T__19) self.state = 291 + self.match(CoreDSL2Parser.T__19) + self.state = 293 self._errHandler.sync(self) _la = self._input.LA(1) if ((((_la - 38)) & ~0x3f) == 0 and ((1 << (_la - 38)) & 6755399441057791) != 0): - self.state = 290 + self.state = 292 localctx.params = self.parameter_list() - self.state = 293 + self.state = 295 self.match(CoreDSL2Parser.T__20) - self.state = 297 + self.state = 299 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 294 + self.state = 296 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 299 + self.state = 301 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 302 + self.state = 304 self._errHandler.sync(self) token = self._input.LA(1) if token in [5]: - self.state = 300 + self.state = 302 localctx.behavior = self.block() pass elif token in [10]: - self.state = 301 + self.state = 303 self.match(CoreDSL2Parser.T__9) pass else: @@ -1825,19 +1825,19 @@ def parameter_list(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 306 + self.state = 308 localctx._parameter_declaration = self.parameter_declaration() localctx.params.append(localctx._parameter_declaration) - self.state = 311 + self.state = 313 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 307 + self.state = 309 self.match(CoreDSL2Parser.T__3) - self.state = 308 + self.state = 310 localctx._parameter_declaration = self.parameter_declaration() localctx.params.append(localctx._parameter_declaration) - self.state = 313 + self.state = 315 self._errHandler.sync(self) _la = self._input.LA(1) @@ -1894,13 +1894,13 @@ def parameter_declaration(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 314 - localctx.type_ = self.type_specifier() self.state = 316 + localctx.type_ = self.type_specifier() + self.state = 318 self._errHandler.sync(self) _la = self._input.LA(1) if _la==96: - self.state = 315 + self.state = 317 localctx.decl = self.declarator() @@ -2294,96 +2294,96 @@ def statement(self): self.enterRule(localctx, 22, self.RULE_statement) self._la = 0 # Token type try: - self.state = 407 + self.state = 409 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,39,self._ctx) if la_ == 1: localctx = CoreDSL2Parser.Block_statementContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 318 + self.state = 320 self.block() pass elif la_ == 2: localctx = CoreDSL2Parser.Procedure_callContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 319 + self.state = 321 localctx.ref = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 320 + self.state = 322 self.match(CoreDSL2Parser.T__19) - self.state = 329 + self.state = 331 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 321 + self.state = 323 localctx._expression = self.expression(0) localctx.args.append(localctx._expression) - self.state = 326 + self.state = 328 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 322 + self.state = 324 self.match(CoreDSL2Parser.T__3) - self.state = 323 + self.state = 325 localctx._expression = self.expression(0) localctx.args.append(localctx._expression) - self.state = 328 + self.state = 330 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 331 + self.state = 333 self.match(CoreDSL2Parser.T__20) - self.state = 332 + self.state = 334 self.match(CoreDSL2Parser.T__9) pass elif la_ == 3: localctx = CoreDSL2Parser.If_statementContext(self, localctx) self.enterOuterAlt(localctx, 3) - self.state = 333 + self.state = 335 localctx.type_ = self.match(CoreDSL2Parser.T__21) - self.state = 334 + self.state = 336 self.match(CoreDSL2Parser.T__19) - self.state = 335 + self.state = 337 localctx._expression = self.expression(0) localctx.cond.append(localctx._expression) - self.state = 336 + self.state = 338 self.match(CoreDSL2Parser.T__20) - self.state = 337 + self.state = 339 localctx._statement = self.statement() localctx.stmt.append(localctx._statement) - self.state = 347 + self.state = 349 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,34,self._ctx) while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: if _alt==1: - self.state = 338 + self.state = 340 self.match(CoreDSL2Parser.T__22) - self.state = 339 + self.state = 341 self.match(CoreDSL2Parser.T__21) - self.state = 340 + self.state = 342 self.match(CoreDSL2Parser.T__19) - self.state = 341 + self.state = 343 localctx._expression = self.expression(0) localctx.cond.append(localctx._expression) - self.state = 342 + self.state = 344 self.match(CoreDSL2Parser.T__20) - self.state = 343 + self.state = 345 localctx._statement = self.statement() localctx.stmt.append(localctx._statement) - self.state = 349 + self.state = 351 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,34,self._ctx) - self.state = 352 + self.state = 354 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,35,self._ctx) if la_ == 1: - self.state = 350 + self.state = 352 self.match(CoreDSL2Parser.T__22) - self.state = 351 + self.state = 353 localctx._statement = self.statement() localctx.stmt.append(localctx._statement) @@ -2393,141 +2393,141 @@ def statement(self): elif la_ == 4: localctx = CoreDSL2Parser.For_statementContext(self, localctx) self.enterOuterAlt(localctx, 4) - self.state = 354 + self.state = 356 localctx.type_ = self.match(CoreDSL2Parser.T__23) - self.state = 355 + self.state = 357 self.match(CoreDSL2Parser.T__19) - self.state = 356 + self.state = 358 localctx.cond = self.for_condition() - self.state = 357 + self.state = 359 self.match(CoreDSL2Parser.T__20) - self.state = 358 + self.state = 360 localctx.stmt = self.statement() pass elif la_ == 5: localctx = CoreDSL2Parser.While_statementContext(self, localctx) self.enterOuterAlt(localctx, 5) - self.state = 360 + self.state = 362 localctx.type_ = self.match(CoreDSL2Parser.T__24) - self.state = 361 + self.state = 363 self.match(CoreDSL2Parser.T__19) - self.state = 362 + self.state = 364 localctx.cond = self.expression(0) - self.state = 363 + self.state = 365 self.match(CoreDSL2Parser.T__20) - self.state = 364 + self.state = 366 localctx.stmt = self.statement() pass elif la_ == 6: localctx = CoreDSL2Parser.Do_statementContext(self, localctx) self.enterOuterAlt(localctx, 6) - self.state = 366 + self.state = 368 localctx.type_ = self.match(CoreDSL2Parser.T__25) - self.state = 367 + self.state = 369 localctx.stmt = self.statement() - self.state = 368 + self.state = 370 self.match(CoreDSL2Parser.T__24) - self.state = 369 + self.state = 371 self.match(CoreDSL2Parser.T__19) - self.state = 370 + self.state = 372 localctx.cond = self.expression(0) - self.state = 371 + self.state = 373 self.match(CoreDSL2Parser.T__20) - self.state = 372 + self.state = 374 self.match(CoreDSL2Parser.T__9) pass elif la_ == 7: localctx = CoreDSL2Parser.Switch_statementContext(self, localctx) self.enterOuterAlt(localctx, 7) - self.state = 374 + self.state = 376 localctx.type_ = self.match(CoreDSL2Parser.T__26) - self.state = 375 + self.state = 377 self.match(CoreDSL2Parser.T__19) - self.state = 376 + self.state = 378 localctx.cond = self.expression(0) - self.state = 377 + self.state = 379 self.match(CoreDSL2Parser.T__20) - self.state = 378 + self.state = 380 self.match(CoreDSL2Parser.T__4) - self.state = 382 + self.state = 384 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,36,self._ctx) while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: if _alt==1: - self.state = 379 + self.state = 381 localctx._switch_block_statement_group = self.switch_block_statement_group() localctx.items.append(localctx._switch_block_statement_group) - self.state = 384 + self.state = 386 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,36,self._ctx) - self.state = 388 + self.state = 390 self._errHandler.sync(self) _la = self._input.LA(1) while _la==32 or _la==33: - self.state = 385 + self.state = 387 self.switch_label() - self.state = 390 + self.state = 392 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 391 + self.state = 393 self.match(CoreDSL2Parser.T__5) pass elif la_ == 8: localctx = CoreDSL2Parser.Return_statementContext(self, localctx) self.enterOuterAlt(localctx, 8) - self.state = 393 - localctx.type_ = self.match(CoreDSL2Parser.T__27) self.state = 395 + localctx.type_ = self.match(CoreDSL2Parser.T__27) + self.state = 397 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 394 + self.state = 396 localctx.expr = self.expression(0) - self.state = 397 + self.state = 399 self.match(CoreDSL2Parser.T__9) pass elif la_ == 9: localctx = CoreDSL2Parser.Break_statementContext(self, localctx) self.enterOuterAlt(localctx, 9) - self.state = 398 + self.state = 400 localctx.type_ = self.match(CoreDSL2Parser.T__28) - self.state = 399 + self.state = 401 self.match(CoreDSL2Parser.T__9) pass elif la_ == 10: localctx = CoreDSL2Parser.Continue_statementContext(self, localctx) self.enterOuterAlt(localctx, 10) - self.state = 400 + self.state = 402 localctx.type_ = self.match(CoreDSL2Parser.T__29) - self.state = 401 + self.state = 403 self.match(CoreDSL2Parser.T__9) pass elif la_ == 11: localctx = CoreDSL2Parser.Spawn_statementContext(self, localctx) self.enterOuterAlt(localctx, 11) - self.state = 402 + self.state = 404 localctx.type_ = self.match(CoreDSL2Parser.T__30) - self.state = 403 + self.state = 405 localctx.stmt = self.statement() pass elif la_ == 12: localctx = CoreDSL2Parser.Expression_statementContext(self, localctx) self.enterOuterAlt(localctx, 12) - self.state = 404 + self.state = 406 localctx.expr = self.expression(0) - self.state = 405 + self.state = 407 self.match(CoreDSL2Parser.T__9) pass @@ -2593,27 +2593,27 @@ def switch_block_statement_group(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 410 + self.state = 412 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 409 + self.state = 411 localctx._switch_label = self.switch_label() localctx.labels.append(localctx._switch_label) - self.state = 412 + self.state = 414 self._errHandler.sync(self) _la = self._input.LA(1) if not (_la==32 or _la==33): break - self.state = 415 + self.state = 417 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 414 + self.state = 416 localctx._statement = self.statement() localctx.statements.append(localctx._statement) - self.state = 417 + self.state = 419 self._errHandler.sync(self) _la = self._input.LA(1) if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417960802517024) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0)): @@ -2665,23 +2665,23 @@ def switch_label(self): localctx = CoreDSL2Parser.Switch_labelContext(self, self._ctx, self.state) self.enterRule(localctx, 26, self.RULE_switch_label) try: - self.state = 425 + self.state = 427 self._errHandler.sync(self) token = self._input.LA(1) if token in [32]: self.enterOuterAlt(localctx, 1) - self.state = 419 + self.state = 421 self.match(CoreDSL2Parser.T__31) - self.state = 420 + self.state = 422 localctx.const_expr = self.expression(0) - self.state = 421 + self.state = 423 self.match(CoreDSL2Parser.T__14) pass elif token in [33]: self.enterOuterAlt(localctx, 2) - self.state = 423 + self.state = 425 self.match(CoreDSL2Parser.T__32) - self.state = 424 + self.state = 426 self.match(CoreDSL2Parser.T__14) pass else: @@ -2739,20 +2739,20 @@ def block(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 427 + self.state = 429 self.match(CoreDSL2Parser.T__4) - self.state = 431 + self.state = 433 self._errHandler.sync(self) _la = self._input.LA(1) while (((_la) & ~0x3f) == 0 and ((1 << _la) & 1149543585831976992) != 0) or ((((_la - 85)) & ~0x3f) == 0 and ((1 << (_la - 85)) & 32575) != 0): - self.state = 428 + self.state = 430 localctx._block_item = self.block_item() localctx.items.append(localctx._block_item) - self.state = 433 + self.state = 435 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 434 + self.state = 436 self.match(CoreDSL2Parser.T__5) except RecognitionException as re: localctx.exception = re @@ -2803,17 +2803,17 @@ def block_item(self): localctx = CoreDSL2Parser.Block_itemContext(self, self._ctx, self.state) self.enterRule(localctx, 30, self.RULE_block_item) try: - self.state = 438 + self.state = 440 self._errHandler.sync(self) token = self._input.LA(1) if token in [5, 20, 22, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 52, 53, 54, 55, 56, 57, 58, 59, 93, 94, 95, 96, 97, 98, 99]: self.enterOuterAlt(localctx, 1) - self.state = 436 + self.state = 438 self.statement() pass elif token in [19, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 85, 86, 87, 88, 89, 90]: self.enterOuterAlt(localctx, 2) - self.state = 437 + self.state = 439 self.declaration() pass else: @@ -2878,55 +2878,55 @@ def for_condition(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 445 + self.state = 447 self._errHandler.sync(self) token = self._input.LA(1) if token in [19, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 85, 86, 87, 88, 89, 90]: - self.state = 440 + self.state = 442 localctx.start_decl = self.declaration() pass elif token in [10, 20, 34, 35, 52, 53, 54, 55, 56, 57, 58, 59, 93, 94, 95, 96, 97, 98, 99]: - self.state = 442 + self.state = 444 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 441 + self.state = 443 localctx.start_expr = self.expression(0) - self.state = 444 + self.state = 446 self.match(CoreDSL2Parser.T__9) pass else: raise NoViableAltException(self) - self.state = 448 + self.state = 450 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 447 + self.state = 449 localctx.end_expr = self.expression(0) - self.state = 450 + self.state = 452 self.match(CoreDSL2Parser.T__9) - self.state = 459 + self.state = 461 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 451 + self.state = 453 localctx._expression = self.expression(0) localctx.loop_exprs.append(localctx._expression) - self.state = 456 + self.state = 458 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 452 + self.state = 454 self.match(CoreDSL2Parser.T__3) - self.state = 453 + self.state = 455 localctx._expression = self.expression(0) localctx.loop_exprs.append(localctx._expression) - self.state = 458 + self.state = 460 self._errHandler.sync(self) _la = self._input.LA(1) @@ -3016,60 +3016,60 @@ def declaration(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 466 + self.state = 468 self._errHandler.sync(self) _la = self._input.LA(1) while _la==19 or _la==49 or ((((_la - 85)) & ~0x3f) == 0 and ((1 << (_la - 85)) & 15) != 0): - self.state = 464 + self.state = 466 self._errHandler.sync(self) token = self._input.LA(1) if token in [19, 87, 88]: - self.state = 461 + self.state = 463 localctx._storage_class_specifier = self.storage_class_specifier() localctx.storage.append(localctx._storage_class_specifier) pass elif token in [85, 86]: - self.state = 462 + self.state = 464 localctx._type_qualifier = self.type_qualifier() localctx.qualifiers.append(localctx._type_qualifier) pass elif token in [49]: - self.state = 463 + self.state = 465 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) pass else: raise NoViableAltException(self) - self.state = 468 + self.state = 470 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 469 + self.state = 471 localctx.type_ = self.type_specifier() - self.state = 478 + self.state = 480 self._errHandler.sync(self) _la = self._input.LA(1) if _la==96: - self.state = 470 + self.state = 472 localctx._declarator = self.declarator() localctx.declarations.append(localctx._declarator) - self.state = 475 + self.state = 477 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 471 + self.state = 473 self.match(CoreDSL2Parser.T__3) - self.state = 472 + self.state = 474 localctx._declarator = self.declarator() localctx.declarations.append(localctx._declarator) - self.state = 477 + self.state = 479 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 480 + self.state = 482 self.match(CoreDSL2Parser.T__9) except RecognitionException as re: localctx.exception = re @@ -3119,17 +3119,17 @@ def type_specifier(self): self.enterRule(localctx, 36, self.RULE_type_specifier) try: self.enterOuterAlt(localctx, 1) - self.state = 482 + self.state = 484 localctx.type_ = self.value_type_specifier() - self.state = 485 + self.state = 487 self._errHandler.sync(self) token = self._input.LA(1) if token in [34]: - self.state = 483 + self.state = 485 localctx.ptr = self.match(CoreDSL2Parser.T__33) pass elif token in [35]: - self.state = 484 + self.state = 486 localctx.ptr = self.match(CoreDSL2Parser.T__34) pass elif token in [4, 10, 21, 96]: @@ -3396,27 +3396,27 @@ def value_type_specifier(self): self.enterRule(localctx, 38, self.RULE_value_type_specifier) self._la = 0 # Token type try: - self.state = 528 + self.state = 530 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,60,self._ctx) if la_ == 1: localctx = CoreDSL2Parser.Integer_typeContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 487 + self.state = 489 localctx.signed = self.integer_signedness() - self.state = 493 + self.state = 495 self._errHandler.sync(self) token = self._input.LA(1) if token in [43, 44, 45, 46]: - self.state = 488 + self.state = 490 localctx.shorthand = self.integer_shorthand() pass elif token in [36]: - self.state = 489 + self.state = 491 self.match(CoreDSL2Parser.T__35) - self.state = 490 + self.state = 492 localctx.size = self.primary() - self.state = 491 + self.state = 493 self.match(CoreDSL2Parser.T__36) pass else: @@ -3427,105 +3427,105 @@ def value_type_specifier(self): elif la_ == 2: localctx = CoreDSL2Parser.Integer_typeContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 495 + self.state = 497 localctx.shorthand = self.integer_shorthand() pass elif la_ == 3: localctx = CoreDSL2Parser.Float_typeContext(self, localctx) self.enterOuterAlt(localctx, 3) - self.state = 496 + self.state = 498 localctx.shorthand = self.float_shorthand() pass elif la_ == 4: localctx = CoreDSL2Parser.Bool_typeContext(self, localctx) self.enterOuterAlt(localctx, 4) - self.state = 497 + self.state = 499 localctx.type_ = self.match(CoreDSL2Parser.T__37) pass elif la_ == 5: localctx = CoreDSL2Parser.Void_typeContext(self, localctx) self.enterOuterAlt(localctx, 5) - self.state = 498 + self.state = 500 localctx.type_ = self.match(CoreDSL2Parser.T__38) pass elif la_ == 6: localctx = CoreDSL2Parser.Composite_declarationContext(self, localctx) self.enterOuterAlt(localctx, 6) - self.state = 499 - localctx.type_ = self.struct_or_union() self.state = 501 + localctx.type_ = self.struct_or_union() + self.state = 503 self._errHandler.sync(self) _la = self._input.LA(1) if _la==96: - self.state = 500 + self.state = 502 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 503 + self.state = 505 self.match(CoreDSL2Parser.T__4) - self.state = 507 + self.state = 509 self._errHandler.sync(self) _la = self._input.LA(1) while ((((_la - 38)) & ~0x3f) == 0 and ((1 << (_la - 38)) & 7177611906123775) != 0): - self.state = 504 + self.state = 506 localctx._struct_declaration = self.struct_declaration() localctx.declarations.append(localctx._struct_declaration) - self.state = 509 + self.state = 511 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 510 + self.state = 512 self.match(CoreDSL2Parser.T__5) pass elif la_ == 7: localctx = CoreDSL2Parser.Composite_referenceContext(self, localctx) self.enterOuterAlt(localctx, 7) - self.state = 512 + self.state = 514 localctx.type_ = self.struct_or_union() - self.state = 513 + self.state = 515 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) pass elif la_ == 8: localctx = CoreDSL2Parser.Enum_declarationContext(self, localctx) self.enterOuterAlt(localctx, 8) - self.state = 515 - localctx.type_ = self.match(CoreDSL2Parser.T__39) self.state = 517 + localctx.type_ = self.match(CoreDSL2Parser.T__39) + self.state = 519 self._errHandler.sync(self) _la = self._input.LA(1) if _la==96: - self.state = 516 + self.state = 518 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 519 + self.state = 521 self.match(CoreDSL2Parser.T__4) - self.state = 520 - self.enumerator_list() self.state = 522 + self.enumerator_list() + self.state = 524 self._errHandler.sync(self) _la = self._input.LA(1) if _la==4: - self.state = 521 + self.state = 523 self.match(CoreDSL2Parser.T__3) - self.state = 524 + self.state = 526 self.match(CoreDSL2Parser.T__5) pass elif la_ == 9: localctx = CoreDSL2Parser.Enum_referenceContext(self, localctx) self.enterOuterAlt(localctx, 9) - self.state = 526 + self.state = 528 localctx.type_ = self.match(CoreDSL2Parser.T__39) - self.state = 527 + self.state = 529 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) pass @@ -3574,7 +3574,7 @@ def integer_signedness(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 530 + self.state = 532 _la = self._input.LA(1) if not(_la==41 or _la==42): self._errHandler.recoverInline(self) @@ -3625,7 +3625,7 @@ def integer_shorthand(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 532 + self.state = 534 _la = self._input.LA(1) if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 131941395333120) != 0)): self._errHandler.recoverInline(self) @@ -3676,7 +3676,7 @@ def float_shorthand(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 534 + self.state = 536 _la = self._input.LA(1) if not(_la==47 or _la==48): self._errHandler.recoverInline(self) @@ -3739,47 +3739,47 @@ def attribute(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 536 + self.state = 538 self.match(CoreDSL2Parser.T__48) - self.state = 537 + self.state = 539 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 551 + self.state = 553 self._errHandler.sync(self) token = self._input.LA(1) if token in [50]: - self.state = 538 + self.state = 540 self.match(CoreDSL2Parser.T__49) - self.state = 539 + self.state = 541 localctx._expression = self.expression(0) localctx.params.append(localctx._expression) pass elif token in [20]: - self.state = 540 + self.state = 542 self.match(CoreDSL2Parser.T__19) - self.state = 541 + self.state = 543 localctx._expression = self.expression(0) localctx.params.append(localctx._expression) - self.state = 546 + self.state = 548 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 542 + self.state = 544 self.match(CoreDSL2Parser.T__3) - self.state = 543 + self.state = 545 localctx._expression = self.expression(0) localctx.params.append(localctx._expression) - self.state = 548 + self.state = 550 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 549 + self.state = 551 self.match(CoreDSL2Parser.T__20) pass elif token in [51]: pass else: pass - self.state = 553 + self.state = 555 self.match(CoreDSL2Parser.T__50) except RecognitionException as re: localctx.exception = re @@ -3833,20 +3833,15 @@ def bit_size_specifier(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 555 + self.state = 557 self.match(CoreDSL2Parser.T__35) - self.state = 556 + self.state = 558 localctx._primary = self.primary() localctx.size.append(localctx._primary) - self.state = 564 + self.state = 566 self._errHandler.sync(self) _la = self._input.LA(1) if _la==4: - self.state = 557 - self.match(CoreDSL2Parser.T__3) - self.state = 558 - localctx._primary = self.primary() - localctx.size.append(localctx._primary) self.state = 559 self.match(CoreDSL2Parser.T__3) self.state = 560 @@ -3857,9 +3852,14 @@ def bit_size_specifier(self): self.state = 562 localctx._primary = self.primary() localctx.size.append(localctx._primary) + self.state = 563 + self.match(CoreDSL2Parser.T__3) + self.state = 564 + localctx._primary = self.primary() + localctx.size.append(localctx._primary) - self.state = 566 + self.state = 568 self.match(CoreDSL2Parser.T__36) except RecognitionException as re: localctx.exception = re @@ -3912,20 +3912,20 @@ def enumerator_list(self): self.enterRule(localctx, 50, self.RULE_enumerator_list) try: self.enterOuterAlt(localctx, 1) - self.state = 568 + self.state = 570 localctx._enumerator = self.enumerator() localctx.enumerators.append(localctx._enumerator) - self.state = 573 + self.state = 575 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,64,self._ctx) while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: if _alt==1: - self.state = 569 + self.state = 571 self.match(CoreDSL2Parser.T__3) - self.state = 570 + self.state = 572 localctx._enumerator = self.enumerator() localctx.enumerators.append(localctx._enumerator) - self.state = 575 + self.state = 577 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,64,self._ctx) @@ -3978,22 +3978,22 @@ def enumerator(self): localctx = CoreDSL2Parser.EnumeratorContext(self, self._ctx, self.state) self.enterRule(localctx, 52, self.RULE_enumerator) try: - self.state = 580 + self.state = 582 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,65,self._ctx) if la_ == 1: self.enterOuterAlt(localctx, 1) - self.state = 576 + self.state = 578 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) pass elif la_ == 2: self.enterOuterAlt(localctx, 2) - self.state = 577 + self.state = 579 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 578 + self.state = 580 self.match(CoreDSL2Parser.T__49) - self.state = 579 + self.state = 581 self.expression(0) pass @@ -4055,25 +4055,25 @@ def struct_declaration(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 582 + self.state = 584 localctx.specifier = self.struct_declaration_specifier() - self.state = 583 + self.state = 585 localctx._declarator = self.declarator() localctx.declarators.append(localctx._declarator) - self.state = 588 + self.state = 590 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 584 + self.state = 586 self.match(CoreDSL2Parser.T__3) - self.state = 585 + self.state = 587 localctx._declarator = self.declarator() localctx.declarators.append(localctx._declarator) - self.state = 590 + self.state = 592 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 591 + self.state = 593 self.match(CoreDSL2Parser.T__9) except RecognitionException as re: localctx.exception = re @@ -4127,17 +4127,17 @@ def struct_declaration_specifier(self): localctx = CoreDSL2Parser.Struct_declaration_specifierContext(self, self._ctx, self.state) self.enterRule(localctx, 56, self.RULE_struct_declaration_specifier) try: - self.state = 595 + self.state = 597 self._errHandler.sync(self) token = self._input.LA(1) if token in [38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 89, 90]: self.enterOuterAlt(localctx, 1) - self.state = 593 + self.state = 595 localctx.type_ = self.type_specifier() pass elif token in [85, 86]: self.enterOuterAlt(localctx, 2) - self.state = 594 + self.state = 596 localctx._type_qualifier = self.type_qualifier() localctx.qualifiers.append(localctx._type_qualifier) pass @@ -4226,41 +4226,41 @@ def declarator(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 597 + self.state = 599 localctx.name = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 604 + self.state = 606 self._errHandler.sync(self) _la = self._input.LA(1) while _la==91: - self.state = 598 + self.state = 600 self.match(CoreDSL2Parser.LEFT_BR) - self.state = 599 + self.state = 601 localctx._expression = self.expression(0) localctx.size.append(localctx._expression) - self.state = 600 + self.state = 602 self.match(CoreDSL2Parser.RIGHT_BR) - self.state = 606 + self.state = 608 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 610 + self.state = 612 self._errHandler.sync(self) _la = self._input.LA(1) while _la==49: - self.state = 607 + self.state = 609 localctx._attribute = self.attribute() localctx.attributes.append(localctx._attribute) - self.state = 612 + self.state = 614 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 615 + self.state = 617 self._errHandler.sync(self) _la = self._input.LA(1) if _la==50: - self.state = 613 + self.state = 615 self.match(CoreDSL2Parser.T__49) - self.state = 614 + self.state = 616 localctx.init = self.initializer() @@ -4315,29 +4315,29 @@ def initializer(self): self.enterRule(localctx, 60, self.RULE_initializer) self._la = 0 # Token type try: - self.state = 625 + self.state = 627 self._errHandler.sync(self) token = self._input.LA(1) if token in [20, 34, 35, 52, 53, 54, 55, 56, 57, 58, 59, 93, 94, 95, 96, 97, 98, 99]: self.enterOuterAlt(localctx, 1) - self.state = 617 + self.state = 619 localctx.expr = self.expression(0) pass elif token in [5]: self.enterOuterAlt(localctx, 2) - self.state = 618 + self.state = 620 self.match(CoreDSL2Parser.T__4) - self.state = 619 - self.initializerList() self.state = 621 + self.initializerList() + self.state = 623 self._errHandler.sync(self) _la = self._input.LA(1) if _la==4: - self.state = 620 + self.state = 622 self.match(CoreDSL2Parser.T__3) - self.state = 623 + self.state = 625 self.match(CoreDSL2Parser.T__5) pass else: @@ -4399,42 +4399,42 @@ def initializerList(self): self.enterRule(localctx, 62, self.RULE_initializerList) try: self.enterOuterAlt(localctx, 1) - self.state = 629 + self.state = 631 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,73,self._ctx) if la_ == 1: - self.state = 627 + self.state = 629 self.designated_initializer() pass elif la_ == 2: - self.state = 628 + self.state = 630 self.initializer() pass - self.state = 638 + self.state = 640 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,75,self._ctx) while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: if _alt==1: - self.state = 631 + self.state = 633 self.match(CoreDSL2Parser.T__3) - self.state = 634 + self.state = 636 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,74,self._ctx) if la_ == 1: - self.state = 632 + self.state = 634 self.designated_initializer() pass elif la_ == 2: - self.state = 633 + self.state = 635 self.initializer() pass - self.state = 640 + self.state = 642 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,75,self._ctx) @@ -4495,22 +4495,22 @@ def designated_initializer(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 642 + self.state = 644 self._errHandler.sync(self) _la = self._input.LA(1) while True: - self.state = 641 + self.state = 643 localctx._designator = self.designator() localctx.designators.append(localctx._designator) - self.state = 644 + self.state = 646 self._errHandler.sync(self) _la = self._input.LA(1) if not (_la==52 or _la==91): break - self.state = 646 + self.state = 648 self.match(CoreDSL2Parser.T__49) - self.state = 647 + self.state = 649 localctx.init = self.initializer() except RecognitionException as re: localctx.exception = re @@ -4568,23 +4568,23 @@ def designator(self): localctx = CoreDSL2Parser.DesignatorContext(self, self._ctx, self.state) self.enterRule(localctx, 66, self.RULE_designator) try: - self.state = 655 + self.state = 657 self._errHandler.sync(self) token = self._input.LA(1) if token in [91]: self.enterOuterAlt(localctx, 1) - self.state = 649 + self.state = 651 self.match(CoreDSL2Parser.LEFT_BR) - self.state = 650 + self.state = 652 localctx.idx = self.expression(0) - self.state = 651 + self.state = 653 self.match(CoreDSL2Parser.RIGHT_BR) pass elif token in [52]: self.enterOuterAlt(localctx, 2) - self.state = 653 + self.state = 655 self.match(CoreDSL2Parser.T__51) - self.state = 654 + self.state = 656 localctx.prop = self.match(CoreDSL2Parser.IDENTIFIER) pass else: @@ -4986,7 +4986,7 @@ def expression(self, _p:int=0): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 688 + self.state = 690 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,81,self._ctx) if la_ == 1: @@ -4994,7 +4994,7 @@ def expression(self, _p:int=0): self._ctx = localctx _prevctx = localctx - self.state = 658 + self.state = 660 self.primary() pass @@ -5002,7 +5002,7 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Deref_expressionContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 659 + self.state = 661 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(_la==52 or _la==53): @@ -5010,7 +5010,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 660 + self.state = 662 localctx.ref = self.match(CoreDSL2Parser.IDENTIFIER) pass @@ -5018,33 +5018,33 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Method_callContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 661 + self.state = 663 localctx.ref = self.match(CoreDSL2Parser.IDENTIFIER) - self.state = 662 + self.state = 664 self.match(CoreDSL2Parser.T__19) - self.state = 671 + self.state = 673 self._errHandler.sync(self) _la = self._input.LA(1) if (((_la) & ~0x3f) == 0 and ((1 << _la) & 1148417956520132608) != 0) or ((((_la - 93)) & ~0x3f) == 0 and ((1 << (_la - 93)) & 127) != 0): - self.state = 663 + self.state = 665 localctx._expression = self.expression(0) localctx.args.append(localctx._expression) - self.state = 668 + self.state = 670 self._errHandler.sync(self) _la = self._input.LA(1) while _la==4: - self.state = 664 + self.state = 666 self.match(CoreDSL2Parser.T__3) - self.state = 665 + self.state = 667 localctx._expression = self.expression(0) localctx.args.append(localctx._expression) - self.state = 670 + self.state = 672 self._errHandler.sync(self) _la = self._input.LA(1) - self.state = 673 + self.state = 675 self.match(CoreDSL2Parser.T__20) pass @@ -5052,7 +5052,7 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Preinc_expressionContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 674 + self.state = 676 localctx.op = self._input.LT(1) _la = self._input.LA(1) if not(_la==54 or _la==55): @@ -5060,7 +5060,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 675 + self.state = 677 localctx.right = self.expression(17) pass @@ -5068,7 +5068,7 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Prefix_expressionContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 676 + self.state = 678 localctx.prefix = self._input.LT(1) _la = self._input.LA(1) if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 216172833653391360) != 0)): @@ -5076,7 +5076,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 677 + self.state = 679 localctx.right = self.expression(16) pass @@ -5084,7 +5084,7 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Prefix_expressionContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 678 + self.state = 680 localctx.prefix = self._input.LT(1) _la = self._input.LA(1) if not(_la==58 or _la==59): @@ -5092,7 +5092,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 679 + self.state = 681 localctx.right = self.expression(15) pass @@ -5100,31 +5100,31 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Cast_expressionContext(self, localctx) self._ctx = localctx _prevctx = localctx - self.state = 680 + self.state = 682 self.match(CoreDSL2Parser.T__19) - self.state = 683 + self.state = 685 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,80,self._ctx) if la_ == 1: - self.state = 681 + self.state = 683 localctx.type_ = self.type_specifier() pass elif la_ == 2: - self.state = 682 + self.state = 684 localctx.sign = self.integer_signedness() pass - self.state = 685 + self.state = 687 self.match(CoreDSL2Parser.T__20) - self.state = 686 + self.state = 688 localctx.right = self.expression(14) pass self._ctx.stop = self._input.LT(-1) - self.state = 745 + self.state = 747 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,84,self._ctx) while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: @@ -5132,18 +5132,18 @@ def expression(self, _p:int=0): if self._parseListeners is not None: self.triggerExitRuleEvent() _prevctx = localctx - self.state = 743 + self.state = 745 self._errHandler.sync(self) la_ = self._interp.adaptivePredict(self._input,83,self._ctx) if la_ == 1: localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 690 + self.state = 692 if not self.precpred(self._ctx, 13): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 13)") - self.state = 691 + self.state = 693 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not((((_la) & ~0x3f) == 0 and ((1 << _la) & 3458764531000410112) != 0)): @@ -5151,7 +5151,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 692 + self.state = 694 localctx.right = self.expression(14) pass @@ -5159,11 +5159,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 693 + self.state = 695 if not self.precpred(self._ctx, 12): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 12)") - self.state = 694 + self.state = 696 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(_la==56 or _la==57): @@ -5171,7 +5171,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 695 + self.state = 697 localctx.right = self.expression(13) pass @@ -5179,11 +5179,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 696 + self.state = 698 if not self.precpred(self._ctx, 11): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 11)") - self.state = 697 + self.state = 699 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(_la==62 or _la==63): @@ -5191,7 +5191,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 698 + self.state = 700 localctx.right = self.expression(12) pass @@ -5199,11 +5199,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 699 + self.state = 701 if not self.precpred(self._ctx, 10): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 10)") - self.state = 700 + self.state = 702 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(((((_la - 36)) & ~0x3f) == 0 and ((1 << (_la - 36)) & 805306371) != 0)): @@ -5211,7 +5211,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 701 + self.state = 703 localctx.right = self.expression(11) pass @@ -5219,11 +5219,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 702 + self.state = 704 if not self.precpred(self._ctx, 9): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 9)") - self.state = 703 + self.state = 705 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(_la==66 or _la==67): @@ -5231,7 +5231,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 704 + self.state = 706 localctx.right = self.expression(10) pass @@ -5239,13 +5239,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 705 + self.state = 707 if not self.precpred(self._ctx, 8): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 8)") - self.state = 706 + self.state = 708 localctx.bop = self.match(CoreDSL2Parser.T__34) - self.state = 707 + self.state = 709 localctx.right = self.expression(9) pass @@ -5253,13 +5253,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 708 + self.state = 710 if not self.precpred(self._ctx, 7): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 7)") - self.state = 709 + self.state = 711 localctx.bop = self.match(CoreDSL2Parser.T__67) - self.state = 710 + self.state = 712 localctx.right = self.expression(8) pass @@ -5267,13 +5267,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 711 + self.state = 713 if not self.precpred(self._ctx, 6): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 6)") - self.state = 712 + self.state = 714 localctx.bop = self.match(CoreDSL2Parser.T__68) - self.state = 713 + self.state = 715 localctx.right = self.expression(7) pass @@ -5281,13 +5281,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 714 + self.state = 716 if not self.precpred(self._ctx, 5): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 5)") - self.state = 715 + self.state = 717 localctx.bop = self.match(CoreDSL2Parser.T__69) - self.state = 716 + self.state = 718 localctx.right = self.expression(6) pass @@ -5295,13 +5295,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Binary_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 717 + self.state = 719 if not self.precpred(self._ctx, 4): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 4)") - self.state = 718 + self.state = 720 localctx.bop = self.match(CoreDSL2Parser.T__70) - self.state = 719 + self.state = 721 localctx.right = self.expression(5) pass @@ -5309,13 +5309,13 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Concat_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 720 + self.state = 722 if not self.precpred(self._ctx, 3): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 3)") - self.state = 721 + self.state = 723 localctx.bop = self.match(CoreDSL2Parser.T__15) - self.state = 722 + self.state = 724 localctx.right = self.expression(4) pass @@ -5323,17 +5323,17 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Conditional_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.cond = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 723 + self.state = 725 if not self.precpred(self._ctx, 2): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 2)") - self.state = 724 + self.state = 726 localctx.bop = self.match(CoreDSL2Parser.T__71) - self.state = 725 + self.state = 727 localctx.then_expr = self.expression(0) - self.state = 726 + self.state = 728 self.match(CoreDSL2Parser.T__14) - self.state = 727 + self.state = 729 localctx.else_expr = self.expression(2) pass @@ -5341,11 +5341,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Assignment_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 729 + self.state = 731 if not self.precpred(self._ctx, 1): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 1)") - self.state = 730 + self.state = 732 localctx.bop = self._input.LT(1) _la = self._input.LA(1) if not(((((_la - 50)) & ~0x3f) == 0 and ((1 << (_la - 50)) & 17171480577) != 0)): @@ -5353,7 +5353,7 @@ def expression(self, _p:int=0): else: self._errHandler.reportMatch(self) self.consume() - self.state = 731 + self.state = 733 localctx.right = self.expression(1) pass @@ -5361,25 +5361,25 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Slice_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.expr = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 732 + self.state = 734 if not self.precpred(self._ctx, 20): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 20)") - self.state = 733 + self.state = 735 localctx.bop = self.match(CoreDSL2Parser.LEFT_BR) - self.state = 734 + self.state = 736 localctx.left = self.expression(0) - self.state = 737 + self.state = 739 self._errHandler.sync(self) _la = self._input.LA(1) if _la==15: - self.state = 735 + self.state = 737 self.match(CoreDSL2Parser.T__14) - self.state = 736 + self.state = 738 localctx.right = self.expression(0) - self.state = 739 + self.state = 741 self.match(CoreDSL2Parser.RIGHT_BR) pass @@ -5387,11 +5387,11 @@ def expression(self, _p:int=0): localctx = CoreDSL2Parser.Postinc_expressionContext(self, CoreDSL2Parser.ExpressionContext(self, _parentctx, _parentState)) localctx.left = _prevctx self.pushNewRecursionContext(localctx, _startState, self.RULE_expression) - self.state = 741 + self.state = 743 if not self.precpred(self._ctx, 18): from antlr4.error.Errors import FailedPredicateException raise FailedPredicateException(self, "self.precpred(self._ctx, 18)") - self.state = 742 + self.state = 744 localctx.op = self._input.LT(1) _la = self._input.LA(1) if not(_la==54 or _la==55): @@ -5402,7 +5402,7 @@ def expression(self, _p:int=0): pass - self.state = 747 + self.state = 749 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,84,self._ctx) @@ -5545,52 +5545,54 @@ def primary(self): localctx = CoreDSL2Parser.PrimaryContext(self, self._ctx, self.state) self.enterRule(localctx, 70, self.RULE_primary) try: - self.state = 759 + self.state = 761 self._errHandler.sync(self) - token = self._input.LA(1) - if token in [96]: + la_ = self._interp.adaptivePredict(self._input,86,self._ctx) + if la_ == 1: localctx = CoreDSL2Parser.Reference_expressionContext(self, localctx) self.enterOuterAlt(localctx, 1) - self.state = 748 + self.state = 750 localctx.ref = self.match(CoreDSL2Parser.IDENTIFIER) pass - elif token in [93, 94, 95, 97]: + + elif la_ == 2: localctx = CoreDSL2Parser.Constant_expressionContext(self, localctx) self.enterOuterAlt(localctx, 2) - self.state = 749 + self.state = 751 localctx.const_expr = self.constant() pass - elif token in [98, 99]: + + elif la_ == 3: localctx = CoreDSL2Parser.Literal_expressionContext(self, localctx) self.enterOuterAlt(localctx, 3) - self.state = 751 + self.state = 753 self._errHandler.sync(self) _alt = 1 while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: if _alt == 1: - self.state = 750 + self.state = 752 localctx._string_literal = self.string_literal() localctx.literal.append(localctx._string_literal) else: raise NoViableAltException(self) - self.state = 753 + self.state = 755 self._errHandler.sync(self) _alt = self._interp.adaptivePredict(self._input,85,self._ctx) pass - elif token in [20]: + + elif la_ == 4: localctx = CoreDSL2Parser.Parens_expressionContext(self, localctx) self.enterOuterAlt(localctx, 4) - self.state = 755 + self.state = 757 self.match(CoreDSL2Parser.T__19) - self.state = 756 + self.state = 758 localctx.expr = self.expression(0) - self.state = 757 + self.state = 759 self.match(CoreDSL2Parser.T__20) pass - else: - raise NoViableAltException(self) + except RecognitionException as re: localctx.exception = re @@ -5641,7 +5643,7 @@ def string_literal(self): self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 761 + self.state = 763 _la = self._input.LA(1) if not(_la==98 or _la==99): self._errHandler.recoverInline(self) @@ -5676,6 +5678,10 @@ def character_constant(self): return self.getTypedRuleContext(CoreDSL2Parser.Character_constantContext,0) + def string_constant(self): + return self.getTypedRuleContext(CoreDSL2Parser.String_constantContext,0) + + def bool_constant(self): return self.getTypedRuleContext(CoreDSL2Parser.Bool_constantContext,0) @@ -5705,27 +5711,32 @@ def constant(self): localctx = CoreDSL2Parser.ConstantContext(self, self._ctx, self.state) self.enterRule(localctx, 74, self.RULE_constant) try: - self.state = 767 + self.state = 770 self._errHandler.sync(self) token = self._input.LA(1) if token in [95]: self.enterOuterAlt(localctx, 1) - self.state = 763 + self.state = 765 self.integer_constant() pass elif token in [94]: self.enterOuterAlt(localctx, 2) - self.state = 764 + self.state = 766 self.floating_constant() pass elif token in [97]: self.enterOuterAlt(localctx, 3) - self.state = 765 + self.state = 767 self.character_constant() pass - elif token in [93]: + elif token in [99]: self.enterOuterAlt(localctx, 4) - self.state = 766 + self.state = 768 + self.string_constant() + pass + elif token in [93]: + self.enterOuterAlt(localctx, 5) + self.state = 769 self.bool_constant() pass else: @@ -5777,7 +5788,7 @@ def integer_constant(self): self.enterRule(localctx, 76, self.RULE_integer_constant) try: self.enterOuterAlt(localctx, 1) - self.state = 769 + self.state = 772 localctx.value = self.match(CoreDSL2Parser.INTEGER) except RecognitionException as re: localctx.exception = re @@ -5825,7 +5836,7 @@ def floating_constant(self): self.enterRule(localctx, 78, self.RULE_floating_constant) try: self.enterOuterAlt(localctx, 1) - self.state = 771 + self.state = 774 localctx.value = self.match(CoreDSL2Parser.FLOAT) except RecognitionException as re: localctx.exception = re @@ -5873,7 +5884,7 @@ def bool_constant(self): self.enterRule(localctx, 80, self.RULE_bool_constant) try: self.enterOuterAlt(localctx, 1) - self.state = 773 + self.state = 776 localctx.value = self.match(CoreDSL2Parser.BOOLEAN) except RecognitionException as re: localctx.exception = re @@ -5921,7 +5932,7 @@ def character_constant(self): self.enterRule(localctx, 82, self.RULE_character_constant) try: self.enterOuterAlt(localctx, 1) - self.state = 775 + self.state = 778 localctx.value = self.match(CoreDSL2Parser.CHARCONST) except RecognitionException as re: localctx.exception = re @@ -5932,6 +5943,54 @@ def character_constant(self): return localctx + class String_constantContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + self.value = None # Token + + def STRING(self): + return self.getToken(CoreDSL2Parser.STRING, 0) + + def getRuleIndex(self): + return CoreDSL2Parser.RULE_string_constant + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterString_constant" ): + listener.enterString_constant(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitString_constant" ): + listener.exitString_constant(self) + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitString_constant" ): + return visitor.visitString_constant(self) + else: + return visitor.visitChildren(self) + + + + + def string_constant(self): + + localctx = CoreDSL2Parser.String_constantContext(self, self._ctx, self.state) + self.enterRule(localctx, 84, self.RULE_string_constant) + try: + self.enterOuterAlt(localctx, 1) + self.state = 780 + localctx.value = self.match(CoreDSL2Parser.STRING) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class Double_left_bracketContext(ParserRuleContext): __slots__ = 'parser' @@ -5968,12 +6027,12 @@ def accept(self, visitor:ParseTreeVisitor): def double_left_bracket(self): localctx = CoreDSL2Parser.Double_left_bracketContext(self, self._ctx, self.state) - self.enterRule(localctx, 84, self.RULE_double_left_bracket) + self.enterRule(localctx, 86, self.RULE_double_left_bracket) try: self.enterOuterAlt(localctx, 1) - self.state = 777 + self.state = 782 self.match(CoreDSL2Parser.LEFT_BR) - self.state = 778 + self.state = 783 self.match(CoreDSL2Parser.LEFT_BR) except RecognitionException as re: localctx.exception = re @@ -6020,12 +6079,12 @@ def accept(self, visitor:ParseTreeVisitor): def double_right_bracket(self): localctx = CoreDSL2Parser.Double_right_bracketContext(self, self._ctx, self.state) - self.enterRule(localctx, 86, self.RULE_double_right_bracket) + self.enterRule(localctx, 88, self.RULE_double_right_bracket) try: self.enterOuterAlt(localctx, 1) - self.state = 780 + self.state = 785 self.match(CoreDSL2Parser.RIGHT_BR) - self.state = 781 + self.state = 786 self.match(CoreDSL2Parser.RIGHT_BR) except RecognitionException as re: localctx.exception = re @@ -6067,11 +6126,11 @@ def accept(self, visitor:ParseTreeVisitor): def data_types(self): localctx = CoreDSL2Parser.Data_typesContext(self, self._ctx, self.state) - self.enterRule(localctx, 88, self.RULE_data_types) + self.enterRule(localctx, 90, self.RULE_data_types) self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 783 + self.state = 788 _la = self._input.LA(1) if not(((((_la - 38)) & ~0x3f) == 0 and ((1 << (_la - 38)) & 70368744179707) != 0)): self._errHandler.recoverInline(self) @@ -6118,11 +6177,11 @@ def accept(self, visitor:ParseTreeVisitor): def type_qualifier(self): localctx = CoreDSL2Parser.Type_qualifierContext(self, self._ctx, self.state) - self.enterRule(localctx, 90, self.RULE_type_qualifier) + self.enterRule(localctx, 92, self.RULE_type_qualifier) self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 785 + self.state = 790 _la = self._input.LA(1) if not(_la==85 or _la==86): self._errHandler.recoverInline(self) @@ -6169,11 +6228,11 @@ def accept(self, visitor:ParseTreeVisitor): def storage_class_specifier(self): localctx = CoreDSL2Parser.Storage_class_specifierContext(self, self._ctx, self.state) - self.enterRule(localctx, 92, self.RULE_storage_class_specifier) + self.enterRule(localctx, 94, self.RULE_storage_class_specifier) self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 787 + self.state = 792 _la = self._input.LA(1) if not(_la==19 or _la==87 or _la==88): self._errHandler.recoverInline(self) @@ -6220,11 +6279,11 @@ def accept(self, visitor:ParseTreeVisitor): def struct_or_union(self): localctx = CoreDSL2Parser.Struct_or_unionContext(self, self._ctx, self.state) - self.enterRule(localctx, 94, self.RULE_struct_or_union) + self.enterRule(localctx, 96, self.RULE_struct_or_union) self._la = 0 # Token type try: self.enterOuterAlt(localctx, 1) - self.state = 789 + self.state = 794 _la = self._input.LA(1) if not(_la==89 or _la==90): self._errHandler.recoverInline(self) diff --git a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Visitor.py b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Visitor.py index 9ad2478d..9702326c 100644 --- a/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Visitor.py +++ b/m2isar/frontends/coredsl2/parser_gen/CoreDSL2Visitor.py @@ -404,6 +404,11 @@ def visitCharacter_constant(self, ctx:CoreDSL2Parser.Character_constantContext): return self.visitChildren(ctx) + # Visit a parse tree produced by CoreDSL2Parser#string_constant. + def visitString_constant(self, ctx:CoreDSL2Parser.String_constantContext): + return self.visitChildren(ctx) + + # Visit a parse tree produced by CoreDSL2Parser#double_left_bracket. def visitDouble_left_bracket(self, ctx:CoreDSL2Parser.Double_left_bracketContext): return self.visitChildren(ctx) diff --git a/m2isar/frontends/coredsl2_set/.gitignore b/m2isar/frontends/coredsl2_set/.gitignore new file mode 100644 index 00000000..92ea2d50 --- /dev/null +++ b/m2isar/frontends/coredsl2_set/.gitignore @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +.antlr +*.jar diff --git a/m2isar/frontends/coredsl2_set/README.md b/m2isar/frontends/coredsl2_set/README.md new file mode 100644 index 00000000..af88943a --- /dev/null +++ b/m2isar/frontends/coredsl2_set/README.md @@ -0,0 +1,81 @@ + + +# CoreDSL 2 Parser + +This parser understands the preliminary version 2 of CoreDSL. Its grammar is implemented after the [original XText grammar](https://github.com/Minres/CoreDSL/blob/master/com.minres.coredsl/src/com/minres/coredsl/CoreDsl.xtext) and the [accompanying programmer's manual](https://github.com/Minres/CoreDSL/wiki/CoreDSL-2-programmer's-manual), as the reference grammar is not complete. + +## Parser generation +The actual text parser for the CoreDSL 2 language is generated from [](CoreDSL2.g4) using the ANTLR4 parser generator. This repository provides up-to-date generation outputs for ease of use. If you want to change the main grammar, you have to regenerate the parser as follows: + +1) Install `antlr-tools` in your venv: + + ``` + pip install antlr-tools + ``` + +2) Run ANTLR4 parser generator: + + ``` + cd /path/to/M2-ISA-R/m2isar/frontends/coredsl2 + antlr4 -v 4.11.1 -o parser_gen -listener -visitor -Dlanguage=Python3 CoreDSL2.g4 + ``` + +A VSCode task for parser generation is already created for this project. To use it, install `antlr-tools` as shown in 1), then select `Terminal` -> `Run Task...` -> `Generate CoreDSL2 ANTLR parser`. + +## Limitations +This parser should be considered as in active development, so bugs will most likely occur. In addition, this parser (but also the metamodel and therefore the code generator) do not implement the following CoreDSL 2 features (at the moment): +- Pre- / Post-increment (`x++, ++x`) +- Switch case statements +- Complex datatypes (`struct`, `enum`) +- Pointers +- `spawn` statements +- String literals + +In addition to that, qualifiers other than `extern` and `register` in `architectural_state` declarations are ignored. The "flexible attribute system" of the reference parser is implemented, although unknown attributes are currently ignored. + +The parser does not honor CoreDSL 2's type promotion rules for arithmetic operations. For progress on this feature, see #10. + +In the future, these features might also be implemented if needed. For most CPU models, they should however not be absolutely necessary. + +Functionality currently considered experimental: +- Slicing expressions +- Concatenation expressions +- Loops + +## Outputs + +The parser outputs the architecture model as a pickled python object at `path/to/input/gen_model/.m2isarmodel`. + +## Usage + +The parser can be called by its full python module path `python -m m2isar.frontends.coredsl2.parser` or if installed as in the main README, simply by `coredsl2_parser`. + +``` +$ coredsl2_parser --help +usage: parser.py [-h] [--log {critical,error,warning,info,debug}] top_level + +positional arguments: + top_level The top-level CoreDSL file. + +optional arguments: + -h, --help show this help message and exit + --log {critical,error,warning,info,debug} +``` + +## Internals +CoreDSL 2 files are parsed using the ANTLR v4 grammar [CoreDSL2.g4](CoreDSL2.g4). Generation of the architecture model takes place during multiple phases: +1) Read top-level CoreDSL file +2) Recursively resolve and read all imports +3) Generate a bottom-up parsing order, to preserve the hierarchical model contained in the CoreDSL description during model generation +4) Parse architectural details and build an architectural model. Here everything except instruction and function behavior is read and generated. +5) Check if top-level architecture model is fully resolved. As CoreDSL 2 allows arbitrary expressions almost anywhere (i.e. user-defined parameters as register size), try to evaluate all expressions describing architectural details. Cancel parsing if evaluation fails. +6) Parse instruction / function behavior, build the behavioral models for each instruction and function. This and the previous parsing steps are seperated to make state tracking between different passes easy. +7) Dump the resulting model to disk, as a binary Python pickle dump. diff --git a/m2isar/frontends/coredsl2_set/__init__.py b/m2isar/frontends/coredsl2_set/__init__.py new file mode 100644 index 00000000..73b72e51 --- /dev/null +++ b/m2isar/frontends/coredsl2_set/__init__.py @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich diff --git a/m2isar/frontends/coredsl2_set/architecture_model_builder.py b/m2isar/frontends/coredsl2_set/architecture_model_builder.py new file mode 100644 index 00000000..9c905281 --- /dev/null +++ b/m2isar/frontends/coredsl2_set/architecture_model_builder.py @@ -0,0 +1,548 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +import itertools +import logging +from typing import Union + +from m2isar import M2DuplicateError, M2NameError, M2TypeError, M2ValueError, flatten +from m2isar.metamodel import arch, behav, intrinsics +from ..coredsl2.parser_gen import CoreDSL2Parser, CoreDSL2Visitor +from .utils import RADIX, SHORTHANDS, SIGNEDNESS + +logger = logging.getLogger("arch_builder") + + +class ArchitectureModelBuilder(CoreDSL2Visitor): + """ANTLR visitor to build an M2-ISA-R architecture model of a CoreDSL 2 specification.""" + + _constants: "dict[str, arch.Constant]" + _instructions: "dict[str, arch.Instruction]" + _functions: "dict[str, arch.Function]" + _always_blocks: "dict[str, arch.AlwaysBlock]" + _instruction_sets: "dict[str, arch.InstructionSet]" + _read_types: "dict[str, str]" + _memories: "dict[str, arch.Memory]" + _memory_aliases: "dict[str, arch.Memory]" + _overwritten_instrs: "list[tuple[arch.Instruction, arch.Instruction]]" + _instr_classes: "set[int]" + _main_reg_file: Union[arch.Memory, None] + + def __init__(self): + super().__init__() + self._constants = {} + self._instructions = {} + self._functions = {} + self._always_blocks = {} + self._instruction_sets = {} + self._read_types = {} + self._memories = {} + self._memory_aliases = {} + + self._overwritten_instrs = [] + self._instr_classes = set() + self._main_reg_file = None + + def visitBit_field(self, ctx: CoreDSL2Parser.Bit_fieldContext): + """Generate a bit field (instruction parameter in encoding).""" + + # generate lower and upper bounds + left = self.visit(ctx.left) + right = self.visit(ctx.right) + + # instantiate M2-ISA-R objects + range = arch.RangeSpec(left.value, right.value) + return arch.BitField(ctx.name.text, range, arch.DataType.U) + + def visitBit_value(self, ctx: CoreDSL2Parser.Bit_valueContext): + """Generate a fixed encoding part.""" + + val = self.visit(ctx.value) + return arch.BitVal(val.bit_size, val.value) + + def visitInstruction_set(self, ctx: CoreDSL2Parser.Instruction_setContext): + """Generate a top-level instruction set object.""" + # print("visitInstruction_set", ctx.name.text) + # print("len(self._constants) 1", len(self._constants)) + # input("22") + + # keep track of seen instruction set names + self._read_types[ctx.name.text] = None + + name = ctx.name.text + extension = [] + if ctx.extension: + extension = [obj.text for obj in ctx.extension] + + # generate flat list of instruction set contents + contents = flatten([self.visit(obj) for obj in ctx.sections]) + # print("len(self._constants) 2", len(self._constants)) + # input("33") + + constants = {} + constants.update(self._constants) + memories = {} + memories.update(self._memories) + functions = {} + functions.update(self._functions) + instructions = {} + # instructions.update(self._instructions) + + # group contents by type + for item in contents: + if isinstance(item, arch.Constant): + constants[item.name] = item + elif isinstance(item, arch.Memory): + memories[item.name] = item + elif isinstance(item, arch.Function): + functions[item.name] = item + item.ext_name = name + elif isinstance(item, arch.Instruction): + instructions[(item.code, item.mask)] = item + item.ext_name = name + elif isinstance(item, arch.AlwaysBlock): + pass + else: + raise M2ValueError("unexpected item encountered") + + # instantiate M2-ISA-R object + i = arch.InstructionSet(name, extension, constants, memories, functions, instructions) + + if name in self._instruction_sets: + raise M2DuplicateError(f'instruction set "{name}" already defined') + + # keep track of instruction set object + self._instruction_sets[name] = i + return i + + def visitSection_instructions(self, ctx: CoreDSL2Parser.Section_instructionsContext): + attributes = dict([self.visit(obj) for obj in ctx.attributes]) + instructions: "list[arch.Instruction]" = [self.visit(obj) for obj in ctx.instructions] + + for attr, val in attributes.items(): + for instr in instructions: + if attr not in instr.attributes: + instr.attributes[attr] = val + + return instructions + + def visitCore_def(self, ctx: CoreDSL2Parser.Core_defContext): + """Generate a top-level CoreDef object.""" + + self.visitChildren(ctx) + + name = ctx.name.text + + c = arch.CoreDef( + name, + list(self._read_types.keys()), + None, + self._constants, + self._memories, + self._memory_aliases, + self._functions, + self._instructions, + self._instr_classes, + intrinsics, + ) + + return c + + def visitSection_arch_state(self, ctx: CoreDSL2Parser.Section_arch_stateContext): + """Generate "archictectural_state" section of CoreDSL file.""" + + decls = [self.visit(obj) for obj in ctx.declarations] + decls = list(itertools.chain.from_iterable(decls)) + for obj in ctx.expressions: + self.visit(obj) + + return decls + + def visitAlways_block(self, ctx: CoreDSL2Parser.Always_blockContext): + """Generate always block""" + + name = ctx.name.text + attributes = dict([self.visit(obj) for obj in ctx.attributes]) + + a = arch.AlwaysBlock(name, attributes, ctx.behavior) + + self._always_blocks[name] = a + + return a + + def visitInstruction(self, ctx: CoreDSL2Parser.InstructionContext): + """Generate non-behavioral parts of an instruction.""" + + # read encoding, attributes and disassembly + encoding = [self.visit(obj) for obj in ctx.encoding] + attributes = dict([self.visit(obj) for obj in ctx.attributes]) + assembly = ctx.assembly.text.replace('"', "") if ctx.assembly is not None else None + mnemonic = ctx.mnemonic.text.replace('"', "") if ctx.mnemonic is not None else None + + i = arch.Instruction(ctx.name.text, attributes, encoding, mnemonic, assembly, ctx.behavior, None) + self._instr_classes.add(i.size) + + instr_id = (i.code, i.mask) + + # check for duplicate instructions + if instr_id in self._instructions: + self._overwritten_instrs.append((self._instructions[instr_id], i)) + + # keep track of instruction + self._instructions[instr_id] = i + + return i + + def visitFunction_definition(self, ctx: CoreDSL2Parser.Function_definitionContext): + """Generate non-behavioral parts of a function.""" + + # decode attributes + attributes = dict([self.visit(obj) for obj in ctx.attributes]) + + if arch.FunctionAttribute.ETISS_TRAP_ENTRY_FN in attributes: + attributes[arch.FunctionAttribute.ETISS_NEEDS_ARCH] = [] + + # decode return type and name + type_ = self.visit(ctx.type_) + name = ctx.name.text + + # decode function arguments + params = [] + if ctx.params: + params = self.visit(ctx.params) + + if not isinstance(params, list): + params = [params] + + return_size = None + data_type = arch.DataType.NONE + + if isinstance(type_, arch.IntegerType): + return_size = type_._width + data_type = arch.DataType.S if type_.signed else arch.DataType.U + + f = arch.Function(name, attributes, return_size, data_type, params, ctx.behavior, ctx.extern is not None) + + # error on duplicate function definition + # TODO: implement overwriting function prototypes? + f2 = self._functions.get(name, None) + + if f2 is not None: + if len(f2.operation.statements) > 0: + raise M2DuplicateError(f'function "{name}" already defined') + + self._functions.pop(name) + + self._functions[name] = f + return f + + def visitParameter_declaration(self, ctx: CoreDSL2Parser.Parameter_declarationContext): + """Generate function argument declaration.""" + + # type is required, name and array size optional + type_ = self.visit(ctx.type_) + name = None + # size = None + if ctx.decl: + if ctx.decl.name: + name = ctx.decl.name.text + if ctx.decl.size: + ctx.decl.size = [self.visit(obj) for obj in ctx.decl.size] + + p = arch.FnParam(name, type_._width, arch.DataType.S if type_.signed else arch.DataType.U) + return p + + def visitInteger_constant(self, ctx: CoreDSL2Parser.Integer_constantContext): + """Generate an integer literal.""" + + # extract raw text + text: str = ctx.value.text.lower() + + # extract tick position for verilog-stlye literal + tick_pos = text.find("'") + + # decode verilog-style literal + if tick_pos != -1: + width = int(text[:tick_pos]) + radix = text[tick_pos + 1] + value = int(text[tick_pos + 2 :], RADIX[radix]) + + # decode normal dec, hex, bin, oct literal + # TODO: remove width inference from text + else: + value = int(text, 0) + if text.startswith("0b"): + width = len(text) - 2 + elif text.startswith("0x"): + width = (len(text) - 2) * 4 + elif text.startswith("0") and len(text) > 1: + width = (len(text) - 1) * 3 + else: + width = value.bit_length() + + return behav.IntLiteral(value, width) + + def visitDeclaration(self, ctx: CoreDSL2Parser.DeclarationContext): + """Generate a declaration.""" + + # extract storage type, qualifiers and attributes + storage = [self.visit(obj) for obj in ctx.storage] + # qualifiers = [self.visit(obj) for obj in ctx.qualifiers] + attributes = dict([self.visit(obj) for obj in ctx.attributes]) + + # extract data type + type_ = self.visit(ctx.type_) + + # extract list of contained declarations for the given type + decls: "list[CoreDSL2Parser.DeclaratorContext]" = ctx.declarations + + ret_decls = [] + + # generate each declaration + for decl in decls: + name = decl.name.text + + # generate a register alias + if type_.ptr == "&": + # error out on duplicate declaration + if name in self._memory_aliases: + raise M2DuplicateError(f"memory {name} already defined") + + # assume default size + size = [1] + # alias needs to have a reference as initializer + init: behav.IndexedReference = self.visit(decl.init) + attributes = {} + + # extract array size + if decl.size: + size = [self.visit(obj).value for obj in decl.size] + + # extract referenced object and indices + left = init.index + right = init.right if init.right is not None else left + reference = init.reference + + if decl.attributes: + attributes = dict([self.visit(obj) for obj in decl.attributes]) + + range = arch.RangeSpec(left, right) + + # if range.length != size[0]: + # raise ValueError(f"range mismatch for \"{name}\"") + + # instantiate M2-ISA-R object, keep track of parent - child relations + m = arch.Memory(name, range, type_._width, attributes) + m.parent = reference + m.parent.children.append(m) + + # keep track of this declaration globally + self._memory_aliases[name] = m + # keep track of this declaration for this declaration statement + ret_decls.append(m) + + # normal declaration + else: + # no storage specifier -> implementation parameter, "Constant" in M2-ISA-R + if len(storage) == 0: + if name in self._constants: + raise M2DuplicateError(f"constant {name} already defined") + + # extract initializer if present + init = None + if decl.init is not None: + init = self.visit(decl.init) + + c = arch.Constant(name, init, [], type_._width, type_.signed) + + self._constants[name] = c + ret_decls.append(c) + + # register and extern declaration: "Memory" object in M2-ISA-R + elif "register" in storage or "extern" in storage: + if name in self._memories: + raise M2DuplicateError(f"memory {name} already defined") + + size = [1] + init = None + attributes = {} + + if decl.size: + size = [self.visit(obj) for obj in decl.size] + + if len(size) > 1: + raise NotImplementedError("arrays with more than one dimension are not supported") + + if decl.init is not None: + init = self.visit(decl.init) + + if decl.attributes: + attributes = dict([self.visit(obj) for obj in decl.attributes]) + + range = arch.RangeSpec(size[0]) + m = arch.Memory(name, range, type_._width, attributes) + + # attach init value to memory object + if init is not None: + m._initval[None] = init.generate(None) + + if arch.MemoryAttribute.IS_MAIN_REG in attributes: + self._main_reg_file = m + + self._memories[name] = m + ret_decls.append(m) + + return ret_decls + + def visitType_specifier(self, ctx: CoreDSL2Parser.Type_specifierContext): + type_ = self.visit(ctx.type_) + if ctx.ptr: + type_.ptr = ctx.ptr.text + return type_ + + def visitInteger_type(self, ctx: CoreDSL2Parser.Integer_typeContext): + """Generate an integer type specification.""" + + # default signedness + signed = True + # minimal integer type is just a signedness without width + width = None + + # extract sign + if ctx.signed is not None: + signed = self.visit(ctx.signed) + + # extract size + if ctx.size is not None: + width = self.visit(ctx.size) + + # extract and decode shorthand (int = signed<32>) + if ctx.shorthand is not None: + width = self.visit(ctx.shorthand) + + # type check width + if isinstance(width, behav.IntLiteral): + width = width.value + elif isinstance(width, behav.NamedReference): + width = width.reference + else: + raise M2TypeError("width has wrong type") + + return arch.IntegerType(width, signed, None) + + def visitVoid_type(self, ctx: CoreDSL2Parser.Void_typeContext): + """Generate a void type.""" + return arch.VoidType(None) + + def visitBool_type(self, ctx: CoreDSL2Parser.Bool_typeContext): + """Generate a bool (alias for unsigned<1>).""" + return arch.IntegerType(1, False, None) + + def visitBinary_expression(self, ctx: CoreDSL2Parser.Binary_expressionContext): + """Generate a binary expression.""" + + # visit LHS and RHS + left = self.visit(ctx.left) + right = self.visit(ctx.right) + op = behav.Operator(ctx.bop.text) + + # return M2-ISA-R object + return behav.BinaryOperation(left, op, right) + + def visitSlice_expression(self, ctx: CoreDSL2Parser.Slice_expressionContext): + left = self.visit(ctx.left) + right = self.visit(ctx.right) if ctx.right is not None else None + expr = self.visit(ctx.expr).reference + + op = behav.IndexedReference(expr, left, right) + return op + + def visitPrefix_expression(self, ctx: CoreDSL2Parser.Prefix_expressionContext): + prefix = behav.Operator(ctx.prefix.text) + expr = self.visit(ctx.right) + return behav.UnaryOperation(prefix, expr) + + def visitReference_expression(self, ctx: CoreDSL2Parser.Reference_expressionContext): + """Generate a referencing expression.""" + + name = ctx.ref.text + + # try to resolve the reference, error out if invalid + ref = self._constants.get(name) or self._memories.get(name) or self._memory_aliases.get(name) + if ref is None: + raise M2NameError(f'reference "{name}" could not be resolved') + return behav.NamedReference(ref) + + def visitStorage_class_specifier(self, ctx: CoreDSL2Parser.Storage_class_specifierContext): + return ctx.children[0].symbol.text + + def visitType_qualifier(self, ctx: CoreDSL2Parser.Type_qualifierContext): + return ctx.children[0].symbol.text + + def visitInteger_signedness(self, ctx: CoreDSL2Parser.Integer_signednessContext): + return SIGNEDNESS[ctx.children[0].symbol.text] + + def visitInteger_shorthand(self, ctx: CoreDSL2Parser.Integer_shorthandContext): + return behav.IntLiteral(SHORTHANDS[ctx.children[0].symbol.text]) + + def visitAssignment_expression(self, ctx: CoreDSL2Parser.Assignment_expressionContext): + """Generate an assignment.""" + + # extract LHS and RHS + left = self.visit(ctx.left) + right = self.visit(ctx.right) + + # if LHS is a reference, assign RHS as its default value + if isinstance(left, behav.NamedReference): + if isinstance(left.reference, arch.Constant): + left.reference.value = right.generate(None) + + elif isinstance(left.reference, arch.Memory): + left.reference._initval[None] = right.generate(None) + + elif isinstance(left, behav.IndexedReference): + left.reference._initval[left.index.generate(None)] = right.generate(None) + + def visitAttribute(self, ctx: CoreDSL2Parser.AttributeContext): + """Generate an attribute.""" + + name = ctx.name.text + + # read attribute from enums + attr = ( + arch.InstrAttribute._member_map_.get(name.upper()) + or arch.MemoryAttribute._member_map_.get(name.upper()) + or arch.FunctionAttribute._member_map_.get(name.upper()) + ) + + # warn if attribute is unknown to M2-ISA-R + if attr is None: + logger.warning('unknown attribute "%s" encountered', name) + attr = name + + return attr, ctx.params + + def visitChildren(self, node): + """Helper method to return flatter results on tree visits.""" + # print("visitChildren", node) + + ret = super().visitChildren(node) + if isinstance(ret, list) and len(ret) == 1: + return ret[0] + return ret + + def aggregateResult(self, aggregate, nextResult): + """Aggregate results from multiple children into a list.""" + + ret = aggregate + if nextResult is not None: + if ret is None: + ret = [nextResult] + else: + ret += [nextResult] + return ret diff --git a/m2isar/frontends/coredsl2_set/behavior_model_builder.py b/m2isar/frontends/coredsl2_set/behavior_model_builder.py new file mode 100644 index 00000000..63c29e7a --- /dev/null +++ b/m2isar/frontends/coredsl2_set/behavior_model_builder.py @@ -0,0 +1,449 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +import logging + +from m2isar import M2NameError, M2SyntaxError, M2TypeError, flatten +from m2isar.metamodel import arch, behav, intrinsics +from m2isar.metamodel.utils import StaticType +from ..coredsl2.parser_gen import CoreDSL2Parser, CoreDSL2Visitor +from .utils import BOOLCONST, RADIX, SHORTHANDS, SIGNEDNESS + +# import seal5.model as seal5_model + +logger = logging.getLogger("behav_builder") + + +class BehaviorModelBuilder(CoreDSL2Visitor): + """ANTLR visitor to build an M2-ISA-R behavioral model of a function or instruction + of a CoreDSL 2 specification. + """ + + def __init__( + self, + constants: "dict[str, arch.Constant]", + memories: "dict[str, arch.Memory]", + memory_aliases: "dict[str, arch.Memory]", + fields: "dict[str, arch.BitFieldDescr]", + functions: "dict[str, arch.Function]", + warned_fns: "set[str]", + ): + super().__init__() + + self._constants = constants + self._memories = memories + self._memory_aliases = memory_aliases + self._fields = fields + self._scalars = {} + self._functions = functions + self.warned_fns = warned_fns if warned_fns is not None else set() + + def visitChildren(self, node): + """Helper method to return flatter results on tree visits.""" + + ret = super().visitChildren(node) + if isinstance(ret, list) and len(ret) == 1: + return ret[0] + return ret + + def aggregateResult(self, aggregate, nextResult): + """Aggregate results from multiple children into a list.""" + + ret = aggregate + if nextResult is not None: + if ret is None: + ret = [nextResult] + else: + ret += [nextResult] + return ret + + def visitProcedure_call(self, ctx: CoreDSL2Parser.Procedure_callContext): + """Generate a procedure (method call without return value) call.""" + + # extract name and reference to procedure object to be called + name = ctx.ref.text + ref = self._functions.get(name, None) + + # error out if method is unknown + if ref is None: + raise M2NameError(f"procedure {name} is not defined") + + # generate method arguments + args = [self.visit(obj) for obj in ctx.args] if ctx.args else [] + + return behav.ProcedureCall(ref, args) + + def visitMethod_call(self, ctx: "CoreDSL2Parser.Method_callContext"): + """Generate a function (method call with return value) call.""" + + # extract name and reference to function object to be called + name = ctx.ref.text + ref = self._functions.get(name, None) + + # error out if method is unknown + if ref is None: + raise M2NameError(f'function "{name}" is not defined') + + if arch.FunctionAttribute.ETISS_TRAP_ENTRY_FN in ref.attributes: + raise M2SyntaxError(f'exception entry function "{name}" must be called as procedure') + + # generate method arguments + args = [self.visit(obj) for obj in ctx.args] if ctx.args else [] + + return behav.FunctionCall(ref, args) + + def visitBlock(self, ctx: CoreDSL2Parser.BlockContext): + """Generate a block of statements, return a list.""" + + items = [self.visit(obj) for obj in ctx.items] + items = list(flatten(items)) + return behav.Block(items) + + def visitDeclaration(self, ctx: CoreDSL2Parser.DeclarationContext): + """Generate a declaration statement. Can be multiple declarations of + the same type at once. Each declaration can have an initial value. + """ + + # extract variable qualifiers, currently unused + # storage = [self.visit(obj) for obj in ctx.storage] + # qualifiers = [self.visit(obj) for obj in ctx.qualifiers] + # attributes = [self.visit(obj) for obj in ctx.attributes] + + type_ = self.visit(ctx.type_) + + decls: "list[CoreDSL2Parser.DeclaratorContext]" = ctx.declarations + + ret_decls = [] + + # iterate over all contained declarations + for decl in decls: + name = decl.name.text + + # instantiate a scalar and its definition + s = arch.Scalar( + name, None, StaticType.NONE, type_.width, arch.DataType.S if type_.signed else arch.DataType.U + ) + self._scalars[name] = s + sd = behav.ScalarDefinition(s) + + # if initializer is present, generate an assignment to apply + # initialization to the scalar + if decl.init: + init = self.visit(decl.init) + else: + init = behav.IntLiteral(0) + + a = behav.Assignment(sd, init) + ret_decls.append(a) + + return ret_decls + + def visitBreak_statement(self, ctx: CoreDSL2Parser.Break_statementContext): + return behav.Break() + + def visitReturn_statement(self, ctx: CoreDSL2Parser.Return_statementContext): + """Generate a return statement.""" + + expr = self.visit(ctx.expr) if ctx.expr else None + return behav.Return(expr) + + def visitWhile_statement(self, ctx: CoreDSL2Parser.While_statementContext): + """Generate a while loop.""" + + stmt = self.visit(ctx.stmt) if ctx.stmt else None + cond = self.visit(ctx.cond) + + if not isinstance(stmt, list): + stmt = [stmt] + + return behav.Loop(cond, stmt, False) + + def visitDo_statement(self, ctx: CoreDSL2Parser.Do_statementContext): + """Generate a do .. while loop.""" + + stmt = self.visit(ctx.stmt) if ctx.stmt else None + cond = self.visit(ctx.cond) + + if not isinstance(stmt, list): + stmt = [stmt] + + return behav.Loop(cond, stmt, True) + + def visitFor_statement(self, ctx: CoreDSL2Parser.For_statementContext): + """Generate a for loop. Currently hacky, untested and mostly broken.""" + + start_decl, start_expr, end_expr, loop_exprs = self.visit(ctx.cond) + stmt = self.visit(ctx.stmt) if ctx.stmt else None + + if not isinstance(stmt, list): + stmt = [stmt] + + ret = [] + + if start_decl is not None: + ret.append(start_decl) + if start_expr is not None: + ret.append(start_expr) + + if loop_exprs: + stmt.extend(loop_exprs) + + ret.append(behav.Loop(end_expr, stmt, False)) + + return ret + + def visitFor_condition(self, ctx: CoreDSL2Parser.For_conditionContext): + """Generate the condition of a for loop.""" + + start_decl = self.visit(ctx.start_decl) if ctx.start_decl else None + start_expr = self.visit(ctx.start_expr) if ctx.start_expr else None + end_expr = self.visit(ctx.end_expr) if ctx.end_expr else None + loop_exprs = [self.visit(obj) for obj in ctx.loop_exprs] if ctx.loop_exprs else None + + return start_decl, start_expr, end_expr, loop_exprs + + def visitIf_statement(self, ctx: CoreDSL2Parser.If_statementContext): + """Generate an if statement. Packs all if, else if and else branches + into one object. + """ + + conds = [self.visit(x) for x in ctx.cond] + stmts = [self.visit(x) for x in ctx.stmt] + + stmts = [x if not isinstance(x, list) else None for x in stmts] + + if None in stmts: + raise Exception("meep") + + return behav.Conditional(conds, stmts) + + def visitConditional_expression(self, ctx: CoreDSL2Parser.Conditional_expressionContext): + """Generate a ternary expression.""" + + cond = self.visit(ctx.cond) + then_expr = self.visit(ctx.then_expr) + else_expr = self.visit(ctx.else_expr) + + return behav.Ternary(cond, then_expr, else_expr) + + def visitBinary_expression(self, ctx: CoreDSL2Parser.Binary_expressionContext): + """Generate a binary expression.""" + + left = self.visit(ctx.left) + op = behav.Operator(ctx.bop.text) + right = self.visit(ctx.right) + + return behav.BinaryOperation(left, op, right) + + def visitPreinc_expression(self, ctx: CoreDSL2Parser.Preinc_expressionContext): + """Generate a pre-increment expression. Not yet supported, throws + :exc:`NotImplementedError`.""" + + raise NotImplementedError("pre-increment expressions are not supported yet") + + def visitPostinc_expression(self, ctx: CoreDSL2Parser.Preinc_expressionContext): + """Generate a post-increment expression. Not yet supported, throws + :exc:`NotImplementedError`.""" + + raise NotImplementedError("post-increment expressions are not supported yet") + + def visitPrefix_expression(self, ctx: CoreDSL2Parser.Prefix_expressionContext): + """Generate an unary expression.""" + + op = behav.Operator(ctx.prefix.text) + right = self.visit(ctx.right) + + return behav.UnaryOperation(op, right) + + def visitParens_expression(self, ctx: CoreDSL2Parser.Parens_expressionContext): + """Generate a parenthesized expression.""" + + expr = self.visit(ctx.expr) + return behav.Group(expr) + + def visitSlice_expression(self, ctx: CoreDSL2Parser.Slice_expressionContext): + """Generate a slice expression. Depending on context, this is translated + to either an actual :class:`m2isar.metamodel.behav.SliceOperation`or + an :class:`m2isar.metamodel.behav.IndexedReference` if a :class:`m2isar.metamodel.arch.Memory + object is to be sliced. + """ + + expr = self.visit(ctx.expr) + + left = self.visit(ctx.left) + right = self.visit(ctx.right) if ctx.right else left + + if ( + isinstance(expr, behav.NamedReference) + and isinstance(expr.reference, arch.Memory) + and (expr.reference.data_range is None or expr.reference.data_range.length > 1) + ): + return behav.IndexedReference(expr.reference, left, right) + else: + return behav.SliceOperation(expr, left, right) + + def visitConcat_expression(self, ctx: CoreDSL2Parser.Concat_expressionContext): + """Generate a concatenation expression.""" + + left = self.visit(ctx.left) + right = self.visit(ctx.right) + + return behav.ConcatOperation(left, right) + + def visitAssignment_expression(self, ctx: CoreDSL2Parser.Assignment_expressionContext): + """Generate an assignment. If a combined arithmetic-assignment is present, + generate an additional binary operation and use it as the RHS. + """ + + op = ctx.bop.text + left = self.visit(ctx.left) + right = self.visit(ctx.right) + + if op != "=": + op2 = behav.Operator(op[:-1]) + right = behav.BinaryOperation(left, op2, right) + + return behav.Assignment(left, right) + + def visitReference_expression(self, ctx: CoreDSL2Parser.Reference_expressionContext): + """Generate a simple reference.""" + + name = ctx.ref.text + + var = ( + self._scalars.get(name) + or self._fields.get(name) + or self._constants.get(name) + or self._memory_aliases.get(name) + or self._memories.get(name) + or intrinsics.get(name) + ) + + if var is None: + raise M2NameError(f'Named reference "{name}" does not exist!') + + return behav.NamedReference(var) + + def visitInteger_constant(self, ctx: CoreDSL2Parser.Integer_constantContext): + """Generate an integer literal.""" + + text: str = ctx.value.text.lower() + + tick_pos = text.find("'") + + if tick_pos != -1: + width = int(text[:tick_pos]) + radix = text[tick_pos + 1] + value = int(text[tick_pos + 2 :], RADIX[radix]) + + else: + value = int(text, 0) + width = value.bit_length() + + return behav.IntLiteral(value, width) + + def visitCharacter_constant(self, ctx: CoreDSL2Parser.Character_constantContext): + """Generate a character literal. Converts directly to uint8.""" + + text: str = ctx.value.text + + value = min(ord(text.replace("'", "")), 255) + + return behav.IntLiteral(value, 8) + + # def visitString_literal(self, ctx:CoreDSL2Parser.String_literalContext): + + # print("visitString_literal", self, ctx, dir(self), dir(ctx)) + # text: str = ctx.value.text + # # text: str = ctx.text + + # return behav.IntLiteral(0, 8) + + def visitString_constant(self, ctx: CoreDSL2Parser.String_constantContext): + # print("visitString_constant", self, ctx, dir(self), dir(ctx)) + text: str = ctx.value.text + assert len(text) >= 2 + assert text[0] == '"' and text[-1] == '"' + text = text[1:-1] + # text: str = ctx.text + + return behav.StringLiteral(text) + # return seal5_model.StringLiteral(text) + + def visitBool_constant(self, ctx: CoreDSL2Parser.Bool_constantContext): + """Generate a boolean literal. Converts directly to uint1.""" + + text: str = ctx.value.text + + return behav.IntLiteral(BOOLCONST[text], 1) + + def visitCast_expression(self, ctx: CoreDSL2Parser.Cast_expressionContext): + """Generate a type cast.""" + + expr = self.visit(ctx.right) + if ctx.type_: + type_ = self.visit(ctx.type_) + sign = arch.DataType.S if type_.signed else arch.DataType.U + size = type_.width + + if ctx.sign: + sign = self.visit(ctx.sign) + sign = arch.DataType.S if sign else arch.DataType.U + size = None + + return behav.TypeConv(sign, size, expr) + + def visitType_specifier(self, ctx: CoreDSL2Parser.Type_specifierContext): + """Generate a generic type specifier.""" + + type_ = self.visit(ctx.type_) + if ctx.ptr: + type_.ptr = ctx.ptr.text + return type_ + + def visitInteger_type(self, ctx: CoreDSL2Parser.Integer_typeContext): + """Generate an integer type specifier.""" + + signed = True + width = None + + if ctx.signed is not None: + signed = self.visit(ctx.signed) + + if ctx.size is not None: + width = self.visit(ctx.size) + + if ctx.shorthand is not None: + width = self.visit(ctx.shorthand) + + if isinstance(width, behav.BaseNode): + width = width.generate(None) + else: + raise M2TypeError("width has wrong type") + + return arch.IntegerType(width, signed, None) + + def visitVoid_type(self, ctx: CoreDSL2Parser.Void_typeContext): + """Generate a void type specifier.""" + + return arch.VoidType(None) + + def visitBool_type(self, ctx: CoreDSL2Parser.Bool_typeContext): + """Generate a bool type specifier. Aliases to unsigned<1>.""" + + return arch.IntegerType(1, False, None) + + def visitInteger_signedness(self, ctx: CoreDSL2Parser.Integer_signednessContext): + """Generate integer signedness.""" + + return SIGNEDNESS[ctx.children[0].symbol.text] + + def visitInteger_shorthand(self, ctx: CoreDSL2Parser.Integer_shorthandContext): + """Lookup a shorthand type specifier.""" + + return behav.IntLiteral(SHORTHANDS[ctx.children[0].symbol.text]) diff --git a/m2isar/frontends/coredsl2_set/expr_interpreter.py b/m2isar/frontends/coredsl2_set/expr_interpreter.py new file mode 100644 index 00000000..bdb9b5d5 --- /dev/null +++ b/m2isar/frontends/coredsl2_set/expr_interpreter.py @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +"""Very crude expression evaluation functions for use during model generation.""" + +from m2isar.metamodel import arch, behav + + +def group(self: behav.Group, context): + return self.expr.generate(context) + + +def int_literal(self: behav.IntLiteral, context): + return self.value + + +def named_reference(self: behav.NamedReference, context): + if isinstance(self.reference, arch.Constant) and self.reference.value is not None: + return self.reference.value + return None + # raise M2ValueError("non-interpretable value encountered") + + +def indexed_reference(self: behav.IndexedReference, context): + idx = self.index.generate(context) + return self.reference._initval[idx] + + +def binary_operation(self: behav.BinaryOperation, context): + left = self.left.generate(context) + right = self.right.generate(context) + if left is None or right is None: + return None + return int(eval(f"{left}{self.op.value}{right}")) + + +def unary_operation(self: behav.UnaryOperation, context): + right = self.right.generate(context) + return int(eval(f"{self.op.value}{right}")) diff --git a/m2isar/frontends/coredsl2_set/importer.py b/m2isar/frontends/coredsl2_set/importer.py new file mode 100644 index 00000000..c5d8bee2 --- /dev/null +++ b/m2isar/frontends/coredsl2_set/importer.py @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +"""Classes to recursively import files of a CoreDSL model.""" + +import logging +import pathlib + +from ..coredsl2.parser_gen import CoreDSL2Listener, CoreDSL2Parser, CoreDSL2Visitor +from .utils import make_parser + + +class Importer(CoreDSL2Listener): + """ANTLR listener based importer. Bad on performance, as it traverses + the entire parse tree when it only has to look for import statements. + """ + + def __init__(self, search_path) -> None: + super().__init__() + self.imported = set() + self.new_children = [] + self.new_defs = [] + self.got_new = True + self.search_path = search_path + + def enterImport_file(self, ctx: CoreDSL2Parser.Import_fileContext): + """The actual import functionality. Extracts the filename to import, + constructs a new parser and parses the next file. + """ + + filename = ctx.RULE_STRING().getText().replace('"', "") + if filename not in self.imported: + print(f"importing file {filename}") + self.got_new = True + self.imported.add(filename) + + parser = make_parser(self.search_path / filename) + + tree = parser.description_content() + + self.new_children.extend(tree.children) + self.new_defs.extend(tree.definitions) + pass + + +def recursive_import(tree, search_path): + """Helper method to recursively process all import statements of a given + parse tree. The search path should be set to the directory of the root document. + """ + + path_extender = ImportPathExtender(search_path) + path_extender.visit(tree) + + importer = VisitImporter(search_path) + + while importer.got_new: + importer.new_imports.clear() + importer.new_defs.clear() + importer.new_children.clear() + importer.got_new = False + + importer.visit(tree) + + tree.imports = importer.new_imports + tree.imports + tree.definitions = importer.new_defs + tree.definitions + tree.children = importer.new_children + [ + x for x in tree.children if not isinstance(x, CoreDSL2Parser.Import_fileContext) + ] + + +class VisitImporter(CoreDSL2Visitor): + """Importer class based on an ANTLR Visitor. Only traverses the model tree + to the import statements and stops traversion after that. + """ + + def __init__(self, search_path) -> None: + super().__init__() + self.imported = set() + self.new_children = [] + self.new_imports = [] + self.new_defs = [] + self.got_new = True + self.search_path = search_path + self.logger = logging.getLogger("visit_importer") + + def visitDescription_content(self, ctx: CoreDSL2Parser.Description_contentContext): + for i in ctx.imports: + self.visit(i) + + def visitImport_file(self, ctx: CoreDSL2Parser.Import_fileContext): + """The actual import functionality. Extracts the filename to import, + constructs a new parser and parses the next file. + """ + + import_name = ctx.uri.text.replace('"', "") + filename = str(pathlib.Path(import_name).resolve()) + + # only import each file once + if filename not in self.imported: + self.logger.info("importing file %s", filename) + + # keep track that we imported something + self.got_new = True + self.imported.add(filename) + + # extract file path and search path + file_path = pathlib.Path(filename) + file_dir = file_path.parent + + parser = make_parser(file_path) + + # run ImportPathExtender on the new tree + tree = parser.description_content() + path_extender = ImportPathExtender(file_dir) + path_extender.visit(tree) + + # keep track of the new children + self.new_children.extend(tree.children) + self.new_imports.extend(tree.imports) + self.new_defs.extend(tree.definitions) + + +class ImportPathExtender(CoreDSL2Visitor): + """ANTLR visitor to resolve relative import paths. Replaces all import URIs + with their equivalent absolute path, relative to search_path. + """ + + def __init__(self, search_path: pathlib.Path) -> None: + super().__init__() + self.search_path = search_path + + def visitDescription_content(self, ctx: CoreDSL2Parser.Description_contentContext): + for i in ctx.imports: + self.visit(i) + + def visitImport_file(self, ctx: CoreDSL2Parser.Import_fileContext): + filename = self.search_path / ctx.uri.text.replace('"', "") + ctx.uri.text = str(filename) diff --git a/m2isar/frontends/coredsl2_set/load_order.py b/m2isar/frontends/coredsl2_set/load_order.py new file mode 100644 index 00000000..d02c81ad --- /dev/null +++ b/m2isar/frontends/coredsl2_set/load_order.py @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +from antlr4 import ParserRuleContext + +from m2isar import M2DuplicateError +from ..coredsl2.parser_gen import CoreDSL2Parser, CoreDSL2Visitor + + +class CoreContainerContext(ParserRuleContext): + pass + + +class LoadOrder(CoreDSL2Visitor): + def __init__(self) -> None: + super().__init__() + self.instruction_sets: "dict[str, CoreDSL2Parser.Instruction_setContext]" = {} + # self.core_defs = {} + self.stacks = {} + + def visitInstruction_set(self, ctx: CoreDSL2Parser.Instruction_setContext): + name = ctx.name.text + # print("set", name, [e.text for e in ctx.extension]) + + if name in self.instruction_sets: + raise M2DuplicateError(f"instruction set {name} specified more than once") + + self.instruction_sets[name] = ctx + stack = [] + for e in ctx.extension: + assert e.text in self.stacks, f"Set not found: {e.text}. Missing include?" + for x in self.stacks[e.text]: + if x not in stack: + stack.append(x) + stack.append(e.text) + self.stacks[name] = stack + # print("stacks", self.stacks) + + # def extend_ins_set(self, ins_set_name): + # if ins_set_name not in self.instruction_sets: + # raise M2NameError(f"instruction set {ins_set_name} is unknown") + + # extensions = [e.text for e in self.instruction_sets[ins_set_name].extension] + # if extensions: + # ret = [ins_set_name] + # for extension in extensions: + # ret = self.extend_ins_set(extension) + ret + # return ret + # else: + # return [ins_set_name] + + # def visitCore_def(self, ctx: CoreDSL2Parser.Core_defContext): + # name = ctx.name.text + # contributing_types = [c.text for c in ctx.contributing_types] + + # ins_set_queue = [] + # known_sets = set() + + # for ct in contributing_types: + # new_sets = self.extend_ins_set(ct) + # for new_set in new_sets: + # if new_set not in known_sets: + # known_sets.add(new_set) + # ins_set_queue.append(self.instruction_sets[new_set]) + + # ins_set_queue.append(ctx) + # self.core_defs[name] = ins_set_queue + + def visit(self, tree): + # print("visit", tree) + _ = super().visit(tree) + + ret = {} + + # for core_name, contents in self.core_defs.items(): + # container = CoreContainerContext() + # container.children = contents + # container.name = core_name + # ret[core_name] = container + for set_name, set_def in self.instruction_sets.items(): + container = CoreContainerContext() + container.children = [self.instruction_sets[x] for x in self.stacks[set_name]] + [set_def] + container.name = set_name + ret[set_name] = container + + return ret diff --git a/m2isar/frontends/coredsl2_set/parser.py b/m2isar/frontends/coredsl2_set/parser.py new file mode 100644 index 00000000..dd06187c --- /dev/null +++ b/m2isar/frontends/coredsl2_set/parser.py @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +import argparse +import itertools +import logging +import pathlib +import pickle +import sys + +from m2isar import M2Error, M2SyntaxError +from m2isar.metamodel import M2_METAMODEL_VERSION, M2Model, behav, patch_model +from m2isar.metamodel.code_info import CodeInfoBase +from . import expr_interpreter +from .architecture_model_builder import ArchitectureModelBuilder +from .behavior_model_builder import BehaviorModelBuilder +from .importer import recursive_import +from .load_order import LoadOrder +from .utils import make_parser + + +def main(): + parser = argparse.ArgumentParser() + parser.add_argument("top_level", help="The CoreDSL file.") + parser.add_argument("--log", default="info", choices=["critical", "error", "warning", "info", "debug"]) + parser.add_argument("--output", "-o", type=str, default=None) + + args = parser.parse_args() + + # app_dir = pathlib.Path(__file__).parent.resolve() + + logging.basicConfig(level=getattr(logging, args.log.upper())) + logger = logging.getLogger("parser") + + top_level = pathlib.Path(args.top_level) + abs_top_level = top_level.resolve() + search_path = abs_top_level.parent + + parser = make_parser(abs_top_level) + + try: + logger.info("parsing top level") + tree = parser.description_content() + + recursive_import(tree, search_path) + except M2SyntaxError as e: + logger.critical("Error during parsing: %s", e) + sys.exit(1) + + logger.info("reading instruction load order") + lo = LoadOrder() + try: + sets = lo.visit(tree) + except M2Error as e: + logger.critical("Error during load order building: %s", e) + sys.exit(1) + + if args.output is None: + model_path = search_path.joinpath("gen_model") + else: + model_path = pathlib.Path(args.output) + model_path.mkdir(exist_ok=True) + + temp_save = {} + + patch_model(expr_interpreter) + + for set_name, set_def in sets.items(): + logger.info(f"building architecture model for set {set_name}") + try: + arch_builder = ArchitectureModelBuilder() + s = arch_builder.visit(set_def) + if not isinstance(s, list): + s = [s] + # print("s", s) + except M2Error as e: + logger.critical("Error building architecture model of core", e) + + for orig, overwritten in arch_builder._overwritten_instrs: + logger.warning( + "instr %s from extension %s was overwritten by %s from %s", + orig.name, + orig.ext_name, + overwritten.name, + overwritten.ext_name, + ) + + temp_save[set_name] = (s, arch_builder) + + sets[set_name] = s[-1] + + for set_name, set_def in sets.items(): + logger.info("building behavior model for set %s", set_name) + # print("set", set_name, set_def, dir(set_def)) + + warned_fns = set() + + logger.debug("checking core constants") + unassigned_const = False + for const in set_def.constants.values(): + # print("const", const) + if const.value is None: + pass + # if const.name == "XLEN": + # if "32" in set_name: + # const.value = 32 + # elif "64" in set_name: + # const.value = 64 + # continue + # logger.critical("constant %s in set %s has no value assigned!", const.name, set_name) + # unassigned_const = True + # sys.exit(-1) + if unassigned_const: + sys.exit(-1) + + logger.debug("evaluating set parameters") + + for const_def in set_def.constants.values(): + const_def._value = const_def.value + + for mem_def in itertools.chain(set_def.memories.values(), set_def.memory_aliases.values()): + mem_def._size = mem_def.size + mem_def.range._lower_base = mem_def.range.lower_base + mem_def.range._upper_base = mem_def.range.upper_base + + for attr_name, attr_ops in mem_def.attributes.items(): + ops = [] + for attr_op in attr_ops: + try: + behav_builder = BehaviorModelBuilder( + set_def.constants, + set_def.memories, + set_def.memory_aliases, + {}, + set_def.functions, + warned_fns, + ) + op = behav_builder.visit(attr_op) + ops.append(op) + except M2Error as e: + logger.critical( + 'error processing attribute "%s" of memory "%s": %s', attr_name, mem_def.name, e + ) + sys.exit(1) + + mem_def.attributes[attr_name] = ops + + for fn_def in set_def.functions.values(): + if isinstance(fn_def.operation, behav.Operation) and not fn_def.extern: + raise M2SyntaxError(f"non-extern function {fn_def.name} has no body") + + fn_def._size = fn_def.size + for fn_arg in fn_def.args.values(): + fn_arg._size = fn_arg.size + fn_arg._width = fn_arg.width + + logger.debug("generating function behavior") + + for fn_name, fn_def in set_def.functions.items(): + logger.debug("generating function %s", fn_name) + logger.debug("generating attributes") + + for attr_name, attr_ops in fn_def.attributes.items(): + ops = [] + for attr_op in attr_ops: + try: + behav_builder = BehaviorModelBuilder( + set_def.constants, + set_def.memories, + set_def.memory_aliases, + fn_def.args, + set_def.functions, + warned_fns, + ) + op = behav_builder.visit(attr_op) + ops.append(op) + except M2Error as e: + logger.critical( + 'error processing attribute "%s" of function "%s": %s', attr_name, fn_def.name, e + ) + sys.exit(1) + + fn_def.attributes[attr_name] = ops + + behav_builder = BehaviorModelBuilder( + set_def.constants, set_def.memories, set_def.memory_aliases, fn_def.args, set_def.functions, warned_fns + ) + + if not isinstance(fn_def.operation, behav.Operation): + try: + op = behav_builder.visit(fn_def.operation) + except M2Error as e: + logger.critical("Error building behavior for function %s: %s", fn_name, e) + sys.exit() + + fn_def.scalars = behav_builder._scalars + + if isinstance(op, list): + fn_def.operation = behav.Operation(op) + else: + fn_def.operation = behav.Operation([op]) + + logger.debug("generating always blocks") + + always_block_statements = [] + + arch_builder = temp_save[set_name][1] + for block_def in arch_builder._always_blocks.values(): + logger.debug("generating always block %s", block_def.name) + logger.debug("generating attributes") + + for attr_name, attr_ops in block_def.attributes.items(): + ops = [] + for attr_op in attr_ops: + try: + behav_builder = BehaviorModelBuilder( + set_def.constants, + set_def.memories, + set_def.memory_aliases, + {}, + set_def.functions, + warned_fns, + ) + op = behav_builder.visit(attr_op) + ops.append(op) + except M2Error as e: + logger.critical( + 'error processing attribute "%s" of instruction "%s": %s', attr_name, block_def.name, e + ) + sys.exit(1) + + block_def.attributes[attr_name] = ops + + behav_builder = BehaviorModelBuilder( + set_def.constants, set_def.memories, set_def.memory_aliases, {}, set_def.functions, warned_fns + ) + + try: + op = behav_builder.visit(block_def.operation) + except M2Error as e: + logger.critical("error building behavior for always block %s: %s", block_def.name, e) + sys.exit(1) + + always_block_statements.append(op) + + logger.debug("generating instruction behavior") + + for instr_def in set_def.instructions.values(): + logger.debug("generating instruction %s", instr_def.name) + logger.debug("generating attributes") + + for attr_name, attr_ops in instr_def.attributes.items(): + ops = [] + for attr_op in attr_ops: + try: + behav_builder = BehaviorModelBuilder( + set_def.constants, + set_def.memories, + set_def.memory_aliases, + instr_def.fields, + set_def.functions, + warned_fns, + ) + op = behav_builder.visit(attr_op) + ops.append(op) + except M2Error as e: + logger.critical( + 'error processing attribute "%s" of instruction "%s": %s', attr_name, instr_def.name, e + ) + sys.exit(1) + + instr_def.attributes[attr_name] = ops + + behav_builder = BehaviorModelBuilder( + set_def.constants, + set_def.memories, + set_def.memory_aliases, + instr_def.fields, + set_def.functions, + warned_fns, + ) + + try: + op = behav_builder.visit(instr_def.operation) + except M2Error as e: + logger.critical( + "error building behavior for instruction %s::%s: %s", instr_def.ext_name, instr_def.name, e + ) + sys.exit(1) + + instr_def.scalars = behav_builder._scalars + + if isinstance(op, list): + op = behav.Operation(op) + else: + op = behav.Operation([op]) + + # pc_inc = behav.Assignment( + # behav.NamedReference(set_def.pc_memory), + # behav.BinaryOperation( + # behav.NamedReference(set_def.pc_memory), + # behav.Operator("+"), + # behav.IntLiteral(int(instr_def.size/8)) + # ) + # ) + + # op.statements.insert(0, pc_inc) + op.statements = always_block_statements + op.statements + instr_def.operation = op + + logger.info("dumping model") + with open(model_path / (abs_top_level.stem + ".m2isarmodel"), "wb") as f: + model_obj = M2Model(M2_METAMODEL_VERSION, {}, sets, CodeInfoBase.database) + pickle.dump(model_obj, f) + + +if __name__ == "__main__": + main() diff --git a/m2isar/frontends/coredsl2_set/utils.py b/m2isar/frontends/coredsl2_set/utils.py new file mode 100644 index 00000000..a3bd7f8b --- /dev/null +++ b/m2isar/frontends/coredsl2_set/utils.py @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# This file is part of the M2-ISA-R project: https://github.com/tum-ei-eda/M2-ISA-R +# +# Copyright (C) 2022 +# Chair of Electrical Design Automation +# Technical University of Munich + +import antlr4 +import antlr4.error.ErrorListener + +from m2isar import M2SyntaxError +from ..coredsl2.parser_gen import CoreDSL2Lexer, CoreDSL2Parser + +RADIX = {"b": 2, "h": 16, "d": 10, "o": 8} + +SHORTHANDS = {"char": 8, "short": 16, "int": 32, "long": 64} + +SIGNEDNESS = {"signed": True, "unsigned": False} + +BOOLCONST = {"true": 1, "false": 0} + + +class MyErrorListener(antlr4.error.ErrorListener.ErrorListener): + def __init__(self, filename=None) -> None: + self.filename = filename + super().__init__() + + def syntaxError(self, recognizer, offendingSymbol, line, column, msg, e): + raise M2SyntaxError(f"Syntax error in file {self.filename}, line {line}, column {column}: {msg}") + + +def make_parser(filename): + input_stream = antlr4.FileStream(filename) + lexer = CoreDSL2Lexer(input_stream) + stream = antlr4.CommonTokenStream(lexer) + parser = CoreDSL2Parser(stream) + error_handler = MyErrorListener(filename) + parser.removeErrorListeners() + parser.addErrorListener(error_handler) + return parser diff --git a/m2isar/metamodel/__init__.py b/m2isar/metamodel/__init__.py index 04eec5cc..e6268df2 100644 --- a/m2isar/metamodel/__init__.py +++ b/m2isar/metamodel/__init__.py @@ -78,7 +78,8 @@ def patch_model(module): @dataclass class M2Model: model_version: int - models: "dict[str, arch.CoreDef]" + cores: "dict[str, arch.CoreDef]" + sets: "dict[str, arch.InstructionSet]" code_infos: "dict[int, code_info.CodeInfoBase]" def __post_init__(self):