Fix potential display coherency problem when D-cache is enabled#455
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pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
Open
Fix potential display coherency problem when D-cache is enabled#455pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
pat-rogers wants to merge 1 commit intoAdaCore:masterfrom
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Fixes the case in which the LTDC displayed content would occasionally
slew to the left and then snap back immediately.
Affects: stm32-dma2d_bitmap, framebuffer_ltdc
DMA2D_Fill_Rect was called without Synchronous => True, allowing DMA2D
writes to the hidden framebuffer to still be in progress when
Internal_Update_Layer flushed and handed the buffer to LTDC. This
caused occasional display corruption ("slewing") as LTDC scanned out
a partially-written buffer.
Fix Fill_Rect to use Synchronous => True, consistent with Fill.
Add Clean_DCache in Internal_Update_Layer covering the hidden buffer
before Set_Frame_Buffer, ensuring CPU-written dirty cache lines are
flushed to physical memory before LTDC DMA reads them.
Author
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Problem remains under at least one as-yet-undetermined circumstance. Investigating further... |
pat-rogers
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Affects: stm32-dma2d_bitmap, framebuffer_ltdc
DMA2D_Fill_Rect was called without Synchronous => True, allowing DMA2D writes to the hidden framebuffer to still be in progress when Internal_Update_Layer flushed and handed the buffer to LTDC. We need to change the call to Fill_Rect to use Synchronous => True, consistent with Fill.
After the calls to Wait_Transfer in procedure Internal_Update_Layer , we need a call to Clean_DCache covering the hidden buffer, before the call to Set_Frame_Buffer, ensuring CPU-written dirty cache lines are flushed to physical memory before LTDC DMA reads them.
Why Wait_Transfer alone is insufficient: Wait_Transfer waits for any in-progress DMA2D transfer to complete on that buffer, and then calls Clean_Invalidate_DCache. That's correct for a buffer the CPU is about to read (invalidate stale CPU-cache lines so it re-fetches DMA2D-written data). But for a buffer LTDC is about to read, we need Clean_DCache (flush CPU-dirty lines to physical memory without discarding them). In other words, Clean_Invalidate is correct for the CPU-read case, and Clean only is correct for the LTDC-handoff case. The Clean_Invalidate_DCache inside Wait_Transfer becomes redundant given the subsequent Clean_DCache, but the synchronization barrier it provides is not. We still need to wait for DMA2D to finish before flipping.