A modular, synthesizable elevator control system implemented in VHDL. This project implements a complete elevator controller with configurable floor count, request handling, and 7-segment display output.
- Configurable Floor Count: Supports up to N floors (default: 10)
- Smart Request Resolution: Maintains a queue of floor requests with automatic clearing on arrival
- Direction Memory: Continues in the current direction when multiple requests exist
- Door Control: Automatic 2-second door open timing at each destination
- Edge Detection: Debounced button inputs using dedicated edge detector modules
- 7-Segment Display: Real-time floor number display on common-anode SSD
- Fully Synthesizable: Clean RTL design suitable for FPGA implementation
The top-level entity that instantiates and connects all sub-modules.
Manages floor requests by registering new requests and clearing them when the elevator arrives.
- Uses edge detectors for button debouncing
- Registers requests on rising edge of
request_btn - Clears floor bit when door opens at that floor
The main FSM that controls elevator movement and door operations.
- 4-state FSM: IDLE, MOVING_UP, MOVING_DOWN, DOOR_OPEN
- 2-second timing for floor transitions and door open
- Direction memory for serving requests efficiently
- Shift-based request detection for above/below floors
A reusable edge detection module for button debouncing.
BCD to 7-segment decoder for common-anode display.
The unit_control module implements the following FSM:
| State | Description | Duration |
|---|---|---|
| IDLE | Waiting for requests | Instant transition |
| MOVING_UP | Traveling upward | 2 seconds per floor |
| MOVING_DOWN | Traveling downward | 2 seconds per floor |
| DOOR_OPEN | Door open at destination | 2 seconds |
vsim -do main.do| Generic | Default | Description |
|---|---|---|
N_FLOORS |
10 | Number of floors in the building |
CLK_FREQ |
50,000,000 | Clock frequency in Hz |
This project is licensed under the MIT License.





