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VHDL Elevator Controller

A modular, synthesizable elevator control system implemented in VHDL. This project implements a complete elevator controller with configurable floor count, request handling, and 7-segment display output.

Features

  • Configurable Floor Count: Supports up to N floors (default: 10)
  • Smart Request Resolution: Maintains a queue of floor requests with automatic clearing on arrival
  • Direction Memory: Continues in the current direction when multiple requests exist
  • Door Control: Automatic 2-second door open timing at each destination
  • Edge Detection: Debounced button inputs using dedicated edge detector modules
  • 7-Segment Display: Real-time floor number display on common-anode SSD
  • Fully Synthesizable: Clean RTL design suitable for FPGA implementation

Architecture Overview

Design

Module Descriptions

1. elevator_ctrl (Top Level)

The top-level entity that instantiates and connects all sub-modules.

2. request_resolver

Manages floor requests by registering new requests and clearing them when the elevator arrives.

  • Uses edge detectors for button debouncing
  • Registers requests on rising edge of request_btn
  • Clears floor bit when door opens at that floor

Request Resolver

3. unit_control

The main FSM that controls elevator movement and door operations.

  • 4-state FSM: IDLE, MOVING_UP, MOVING_DOWN, DOOR_OPEN
  • 2-second timing for floor transitions and door open
  • Direction memory for serving requests efficiently
  • Shift-based request detection for above/below floors

4. EdgeDetector

A reusable edge detection module for button debouncing.

5. DisplayDecoder

BCD to 7-segment decoder for common-anode display.

State Machine

The unit_control module implements the following FSM:

State Diagram

State Descriptions

State Description Duration
IDLE Waiting for requests Instant transition
MOVING_UP Traveling upward 2 seconds per floor
MOVING_DOWN Traveling downward 2 seconds per floor
DOOR_OPEN Door open at destination 2 seconds

RTL Diagrams

Request Resolver RTL

Request Resolver RTL

Unit Control RTL

Unit Control RTL

Simulation Waveforms

Functional Simulation

Waveform

Simulation

vsim -do main.do

⚙️ Parameters

Generic Default Description
N_FLOORS 10 Number of floors in the building
CLK_FREQ 50,000,000 Clock frequency in Hz

License

This project is licensed under the MIT License.

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A modular, synthesizable elevator control system implemented in VHDL with configurable floor count, request handling, FSM-based control, and 7-segment display output for FPGA implementation

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