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[#17126][fix] Align FP8 block-scales Python gates with C++ SM121 aliasing - #17166

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DhineshPonnarasan:fix/sm121-fp8-block-scales-gate-alignment
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[#17126][fix] Align FP8 block-scales Python gates with C++ SM121 aliasing#17166
DhineshPonnarasan wants to merge 3 commits into
NVIDIA:mainfrom
DhineshPonnarasan:fix/sm121-fp8-block-scales-gate-alignment

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@DhineshPonnarasan DhineshPonnarasan commented Aug 1, 2026

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Background

On SM121 (GB10/DGX Spark), the C++ getSMVersion() in cudaUtils.h aliases SM121→120, so the C++ kernel correctly runs the SM120 code path. However, Python get_sm_version() returns 121, causing Python to select the wrong branch. This produces a scale-layout mismatch error (Scale dtype must be Int32.) on dense/MLA FP8 block-scales paths.

Changes

Changed all Python FP8 block-scales gates from get_sm_version() == 120 to get_sm_version() in (120, 121) across 7 files:

  • tensorrt_llm/_torch/modules/linear.py (2 sites)
  • tensorrt_llm/_torch/modules/attention.py (1 site)
  • tensorrt_llm/_torch/auto_deploy/custom_ops/quantization/torch_quant.py (1 site)
  • tensorrt_llm/_torch/modules/fused_moe/fused_moe_cutlass.py (2 sites + FP8_BLOCK_SCALES sm_constraint set and comment)
  • tensorrt_llm/_torch/modules/fused_moe/quantization.py (1 site)
  • tensorrt_llm/_torch/models/modeling_deepseekv3.py (1 site)
  • tensorrt_llm/_torch/models/modeling_glm.py (1 site)

No C++ changes are needed since the aliasing already exists in cpp/include/tensorrt_llm/common/cudaUtils.h.

Verification

Requires an SM121 machine to confirm the forward pass no longer raises Scale dtype must be Int32. and that get_sm_version() returns 121 while the SM120 code path is correctly selected.

…15503

Add a debug-only instrumentation gated on the TRTLLM_DIFF_TRACE
environment variable. When enabled, the Attention.forward method
saves the last-token slice of six priority tensors at layer 0
during context (prefill) forwards and compares each new save
against the first context forward (Run 1).

Saved tensors in priority order:
  A_qkv          - self.qkv_proj output
  B_q, B_k, B_v  - q,k,v immediately before the attention backend
  C_attn_output  - attention backend output
  D_o_proj       - o_proj output

When the first differing tensor is found, later-priority tensors
are skipped to minimize trace overhead. When TRTLLM_DIFF_TRACE is
not set, the hooks early-exit with a single bool check and no
GPU or disk I/O is performed.

Signed-off-by: Dhinesh Ponnarasan <dhineshponnarasan@gmail.com>
@DhineshPonnarasan DhineshPonnarasan changed the title [fix] Align FP8 block-scales Python gates with C++ SM121 aliasing [NVBUG/17126][fix] Align FP8 block-scales Python gates with C++ SM121 aliasing Aug 1, 2026
@DhineshPonnarasan DhineshPonnarasan changed the title [NVBUG/17126][fix] Align FP8 block-scales Python gates with C++ SM121 aliasing [#17126][fix] Align FP8 block-scales Python gates with C++ SM121 aliasing Aug 1, 2026
@DhineshPonnarasan
DhineshPonnarasan force-pushed the fix/sm121-fp8-block-scales-gate-alignment branch from 7c2b6e7 to 41a1e85 Compare August 1, 2026 21:59
On GB10 (SM121), C++ getSMVersion() aliases 121 to 120 so the C++
kernel runs the SM120 code path, but Python get_sm_version() returns
121, causing Python to select the wrong branch. This produces a
scale-layout mismatch (Scale dtype must be Int32. on dense/MLA paths).

Change all Python FP8 block-scales gates from
  get_sm_version() == 120
to
  get_sm_version() in (120, 121)

so Python and C++ agree on which code path to use.

Fixes: NVIDIA#17126
Signed-off-by: Dhinesh Ponnarasan <dhineshponnarasan@gmail.com>
@DhineshPonnarasan
DhineshPonnarasan force-pushed the fix/sm121-fp8-block-scales-gate-alignment branch from 41a1e85 to 7c9ab2c Compare August 1, 2026 22:04
Signed-off-by: Dhinesh Ponnarasan <160256912+DhineshPonnarasan@users.noreply.github.com>
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