Move the DSv4 MI355X SGLang AgentX arm to sgl-dev v0.5.18 and split TP4/TP8 by concurrency - #2710
Move the DSv4 MI355X SGLang AgentX arm to sgl-dev v0.5.18 and split TP4/TP8 by concurrency#2710karverma-amd wants to merge 3 commits into
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Ports the image and serving flags validated on the AMD fork onto this key. Runner and search space are unchanged. - image: lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260813 -> rocm/sgl-dev:v0.5.18-rocm720-mi35x-20260822 - enable the DSv4 kernel fusions the new image carries, all default off in environ.py: SGLANG_OPT_USE_AITER_BATCHED_GEMM, SGLANG_OPT_NATIVE_BPRESHUFFLE_SCALE and SGLANG_OPT_FUSE_COMPRESS_NORM_ROPE - mem-fraction-static 0.85 -> 0.89 to enlarge the full-attention KV pool, keeping enough remainder for the compressor state pools that are allocated after it - --disable-shared-experts-fusion -> --enforce-shared-experts-fusion; the tuned MoE tables in this image cover the resulting (inter_dim 384, expert 385, topk 7) shape at the token sizes this workload hits The stale comment claiming the image matches the disagg AgentX entry is updated; that key is still on v0.5.17-20260817. Co-authored-by: Cursor <cursoragent@cursor.com>
TP4 owns the low-concurrency end at [1, 2, 4, 8, 10] with no host KV tier, where halving the GPUs per replica raises throughput per GPU. The TP8 no-offload arm drops from [1, 2, 4, 8, 16] to [16], so TP8 picks up where TP4 leaves off instead of duplicating those points. conc 16 still appears on both TP8 arms to isolate the host KV tier's gain. This removes the published TP8 concurrency 1, 2, 4 and 8 points and adds TP4 concurrency 1, 2, 4, 8 and 10. TP4 doubles per-rank weights and leaves far less room for KV, which is why it stops at concurrency 10 and ships no hicache variant. The comment's "pure TP8 only" phrasing is updated to "tensor-parallel only", which is what it meant - the exclusion is DP-attention, not TP4. Co-authored-by: Cursor <cursoragent@cursor.com>
![claude[bot]](https://avatars.githubusercontent.com/in/1236702?s=60&v=4){kind=small}
Co-authored-by: Cursor <cursoragent@cursor.com>
![cursor[bot]](https://avatars.githubusercontent.com/in/1210556?s=60&v=4){kind=small}
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Reviewed by Cursor Bugbot for commit 9a0194c. Configure here.
| # DSv4 kernel fusions carried by the sgl-dev image: aiter batched GEMM for the | ||
| # absorbed MLA projections, native b-preshuffle scale handling, and a fused | ||
| # compress+norm+rope epilogue. All three default off in environ.py. | ||
| export SGLANG_OPT_USE_AITER_BATCHED_GEMM=1 |
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Missing aiter master switch
Medium Severity
SGLANG_OPT_USE_AITER_BATCHED_GEMM is enabled to route the DSv4 MLA absorb GEMM through aiter, but SGLANG_USE_AITER is never set. Sibling MI355X recipes and the multi-node DSv4 env export that master switch; without it the batched-GEMM path typically stays inactive, so the advertised fusion does not take effect.
Reviewed by Cursor Bugbot for commit 9a0194c. Configure here.
1am9trash
added
AMD
full-sweep-enabled
agentx
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Dispatched trusted sweep run for approved external revision 已为获批的外部提交 |
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Sglang cookbook update PR for inferneceX is ready. |
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Summary
Updates
dsv4-fp4-mi355x-sglang-agentic-mtpto the image and serving flags validated on the AMD fork, and splits the search space so TP4 covers the low-concurrency end.Image and serving flags (
a3feffec)lmsysorg/sglang-rocm:v0.5.17-rocm720-mi35x-20260813→rocm/sgl-dev:v0.5.18-rocm720-mi35x-20260822environ.py:SGLANG_OPT_USE_AITER_BATCHED_GEMM,SGLANG_OPT_NATIVE_BPRESHUFFLE_SCALE,SGLANG_OPT_FUSE_COMPRESS_NORM_ROPEmem-fraction-static0.85 → 0.89, enlarging the full-attention KV pool. The DSv4 compressor state pools are sized from that pool and allocated after it, outside this budget, so the remainder still has to cover them — which is why this stops short of 0.90.--disable-shared-experts-fusion→--enforce-shared-experts-fusion. The tuned MoE tables in this image cover the resulting(inter_dim 384, expert 385, topk 7)shape at the token sizes this workload hits; on the previous image that shape fell back to a heuristic FlyDSL kernel.Search space (
5823400)[1, 2, 4, 8, 10]with no host KV tier, where halving the GPUs per replica raises throughput per GPU[1, 2, 4, 8, 16]to[16], so TP8 picks up where TP4 leaves off rather than duplicating those points[16, 32, 48], and concurrency 16 still appears on both TP8 arms to isolate the host KV tier's gain.TP4 doubles per-rank weights and leaves far less room for KV, which is why it stops at concurrency 10 and ships no hicache variant.
The
runner(cluster:mi355x-amds) is unchanged, and no directory structure changed.Also corrects a comment that claimed the image matched the disagg AgentX entry — that key is still on
v0.5.17-...-20260817— and rewords "pure TP8 only" to "tensor-parallel only", which is what it meant: the exclusion is DP-attention, not TP4.Test plan
bash -n benchmarks/single_node/agentic/dsv4_fp4_mi355x_sglang_mtp.shconfigs/amd-master.yamlandperf-changelog.yamlboth parseprocess_changelog.py --base-ref main --head-ref HEADtriggers all 9 cells plus the conc-48 agentic evalMade with Cursor