A simple but cycle-accurate RISC-V simulator designed by Drexel DISCO Lab.
This (incomplete) simulator is for ECEC 355 course projects.

P.I.s: Dr. Anup Das, Dr. Nagarajan Kandasamy

Course Projects Based on DREXEL-DISCO-RISC-V-Simulator:
(1) Single-cycle RISC-V Simulation with Exploration to Multi-core System
(2) Pipelining RISC-V Simulation with Data Forwarding

To compile:
bash compile.bash single-cycle OR
bash compile.bash pipeline

To run single-cycle:
./RVSim configs/RISC_V.cfg out/out cpu_traces/cpu_traces_core_0

To run pipeline (only support R-type as an example for students):
./RVSim configs/RISC_V.cfg out/out cpu_traces/pipeline_debugging_with_hazard

For more information, please review course_projects section. We are currently developing C version, will update soon.