jpeg_rle: Add missing reset to ddstrb pipeline register to prevent spurious go after reset

[ashnaaseth2325-oss]

SUMMARY

This PR adds a missing asynchronous reset to the ddstrb pipeline register in jpeg_rle.v, preventing invalid signal propagation after reset. The change affects the jpeg_rle module and ensures stable interaction with jpeg_rle1 by eliminating unintended go pulses.

---

FIX

// Before
always @(posedge clk)
  ddstrb <= #1 dstrb;

// After
always @(posedge clk or negedge rst)
  if (!rst)
    ddstrb <= #1 1'b0;
  else
    ddstrb <= #1 dstrb;

---

VERIFICATION

Simulate with rst deasserted while dstrb is high or unknown; previously this caused an immediate transition to ac state with invalid outputs. After the fix, ddstrb resets to 0 and no spurious go pulse occurs. The state machine remains in dc until valid input arrives, preserving correct JPEG block encoding.

[maliberty]

This change leads to a small QOR change. Please run update_ok for this design and commit the updated rules file. That should get the CI passing.

[ashnaaseth2325-oss]

Hello @maliberty,
Thanks! This change affects QoR as expected.
I’m currently unable to run the full OpenROAD flow locally due to tool setup issues, and I also don’t have access to Jenkins artifacts.
Could you please run update_ok and commit the updated rules?
Happy to rebase if needed.