store original pin names during mbff clustering, add regressions,

src/gpl/src/mbff.cpp

@@ -861,18 +861,27 @@ void MBFF::ModifyPinConnections(const std::vector<Flop>& flops,
       }
     }
 
-    // disconnect / reconnect iterms
+    // Classify each original iterm and record its tray-port mapping
+    // *before* disconnecting, then disconnect/reconnect and store the
+    // original pin name as a property on the tray instance.
+    const std::string orig_inst_name(insts_[flops[i].idx]->getName());
     for (dbITerm* iterm : insts_[flops[i].idx]->getITerms()) {
+      // Classify while the iterm is still connected.
+      const bool is_d = IsDPin(iterm);
+      const bool is_q = !is_d && IsQPin(iterm);
+      const bool is_qn_inv = is_q && IsInvertingQPin(iterm);
+      const std::string orig_port_name = iterm->getMTerm()->getName();
+
       dbNet* net = iterm->getNet();
       while (net) {
         iterm->disconnect();
 
         // standard pins
-        if (IsDPin(iterm)) {
+        if (is_d) {
           tray_inst[tray_idx]->findITerm(d_pin->name().c_str())->connect(net);
         }
-        if (IsQPin(iterm)) {
-          if (IsInvertingQPin(iterm)) {
+        if (is_q) {
+          if (is_qn_inv) {
             tray_inst[tray_idx]
                 ->findITerm(qn_pin->name().c_str())
                 ->connect(net);
@@ -914,6 +923,31 @@ void MBFF::ModifyPinConnections(const std::vector<Flop>& flops,
 
         net = iterm->getNet();
       }
+
+      // Store original FF→tray pin mapping as a property on the tray
+      // instance so timing reports can display the original pin name.
+      std::string tray_port;
+      if (is_d && d_pin) {
+        tray_port = d_pin->name();
+      } else if (is_q) {
+        if (is_qn_inv && qn_pin) {
+          tray_port = qn_pin->name();
+        } else if (q_pin) {
+          tray_port = q_pin->name();
+        }
+      }
+      if (!tray_port.empty()) {
+        const std::string key = "orig_name_" + tray_port;
+        const std::string val = orig_inst_name + "/" + orig_port_name;
+        odb::dbStringProperty* prop
+            = odb::dbStringProperty::find(tray_inst[tray_idx], key.c_str());
+        if (prop) {
+          prop->setValue(val.c_str());
+        } else {
+          odb::dbStringProperty::create(
+              tray_inst[tray_idx], key.c_str(), val.c_str());
+        }
+      }
     }
   }
 

src/gpl/test/CMakeLists.txt

@@ -7,6 +7,7 @@ or_integration_tests(
     clust02
     clust03
     cluster_place01
+    mbff_orig_name
     convergence01
     core01
     density01

src/gpl/test/mbff_orig_name.def

@@ -0,0 +1,41 @@
+VERSION 5.8 ;
+DIVIDERCHAR "/" ;
+BUSBITCHARS "[]" ;
+DESIGN tray_test ;
+UNITS DISTANCE MICRONS 1000 ;
+DIEAREA ( 0 0 ) ( 10000 10000 ) ;
+
+
+COMPONENTS 4 ;
+- ff1 DFFHQNx1_ASAP7_75t_L + PLACED ( 6000 6000 ) N ;
+- ff2 DFFHQNx1_ASAP7_75t_L + PLACED ( 4000 6000 ) N ;
+- ff3 DFFHQNx1_ASAP7_75t_L + PLACED ( 4000 4000 ) N ;
+- ff4 DFFHQNx1_ASAP7_75t_L + PLACED ( 6000 4000 ) N ;
+END COMPONENTS
+
+PINS 1 ;
+- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 0 0 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- d1 + NET d1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 360 0 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- d2 + NET d2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 540 0 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- d3 + NET d3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 720 0 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- d4 + NET d4 + DIRECTION INPUT + USE SIGNAL + FIXED ( 900 0 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- o1 + NET o1 + DIRECTION INPUT + USE SIGNAL + FIXED ( 360 10000 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- o2 + NET o2 + DIRECTION INPUT + USE SIGNAL + FIXED ( 540 10000 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- o3 + NET o3 + DIRECTION INPUT + USE SIGNAL + FIXED ( 720 10000 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+- o4 + NET o4 + DIRECTION INPUT + USE SIGNAL + FIXED ( 900 10000 ) N + LAYER M1 ( 0 0 ) ( 180 180 ) ;
+END PINS
+
+
+NETS 1 ;
+- clk1 ( PIN clk1 ) ( ff1 CLK ) ( ff2 CLK ) ( ff3 CLK ) ( ff4 CLK ) + USE SIGNAL ;
+- d1 ( PIN d1 ) ( ff1 D ) + USE SIGNAL ;
+- d2 ( PIN d2 ) ( ff2 D ) + USE SIGNAL ;
+- d3 ( PIN d3 ) ( ff3 D ) + USE SIGNAL ;
+- d4 ( PIN d4 ) ( ff4 D ) + USE SIGNAL ;
+- o1 ( PIN o1 ) ( ff1 QN ) + USE SIGNAL ;
+- o2 ( PIN o2 ) ( ff2 QN ) + USE SIGNAL ;
+- o3 ( PIN o3 ) ( ff3 QN ) + USE SIGNAL ;
+- o4 ( PIN o4 ) ( ff4 QN ) + USE SIGNAL ;
+END NETS
+
+END DESIGN

src/gpl/test/mbff_orig_name.ok

@@ -0,0 +1,45 @@
+[INFO ODB-0227] LEF file: ./asap7/asap7_tech_1x_201209.lef, created 30 layers, 9 vias
+[INFO ODB-0227] LEF file: ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef, created 212 library cells
+[INFO ODB-0227] LEF file: ./2BitTrayH2/asap7sc7p5t_DFFHQNV2X.lef, created 9 library cells
+[INFO ODB-0394] Duplicate site asap7sc7p5t_pg in asap7sc7p5t_DFFHQNV4X already seen in asap7sc7p5t_DFFHQNV2X
+[INFO ODB-0227] LEF file: ./4BitTrayH4/asap7sc7p5t_DFFHQNV4X.lef, created 9 library cells
+[INFO ODB-0394] Duplicate site asap7sc7p5t_pg in asap7sc7p5t_DFFHQNH2V2X already seen in asap7sc7p5t_DFFHQNV2X
+[INFO ODB-0227] LEF file: ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X.lef, created 9 library cells
+[INFO ODB-0128] Design: tray_test
+[INFO ODB-0130]     Created 9 pins.
+[INFO ODB-0131]     Created 4 components and 20 component-terminals.
+[INFO ODB-0133]     Created 9 nets and 12 connections.
+Alpha = 40.0, Beta = 1.0, #paths = 0, max size = -1
+Total ILP Cost: 97.228
+Total Timing Critical Path Displacement: 0.0
+Average slot-to-flop displacement: 0.865
+Final Objective Value: 97.228
+Sizes used
+  2-bit: 2
+Startpoint: d1 (input port clocked by clk)
+Endpoint: _tray_size2_7 (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+
+  Delay    Time   Description                          Orig Name
+---------------------------------------------------------------------------------------------
+   0.00    0.00   clock clk (rise edge)
+   0.00    0.00   clock network delay (ideal)
+   0.00    0.00 ^ input external delay
+   0.00    0.00 ^ d1 (in)
+   0.00    0.00 ^ _tray_size2_7/D1 (DFFHQNV2Xx1_ASAP7_75t_L) ff1/D
+           0.00   data arrival time
+
+1000.00 1000.00   clock clk (rise edge)
+   0.00 1000.00   clock network delay (ideal)
+   0.00 1000.00   clock reconvergence pessimism
+        1000.00 ^ _tray_size2_7/CLK (DFFHQNV2Xx1_ASAP7_75t_L)
+ -22.99  977.01   library setup time
+         977.01   data required time
+---------------------------------------------------------------------------------------------
+         977.01   data required time
+          -0.00   data arrival time
+---------------------------------------------------------------------------------------------
+         977.01   slack (MET)
+
+

src/gpl/test/mbff_orig_name.tcl

@@ -0,0 +1,29 @@
+source helpers.tcl
+set test_name mbff_orig_name
+
+read_lef ./asap7/asap7_tech_1x_201209.lef
+read_lef ./SingleBit/asap7sc7p5t_28_L_1x_220121a.lef
+read_lib ./SingleBit/asap7sc7p5t_SEQ_LVT_TT_nldm_220123.lib
+
+read_lef ./2BitTrayH2/asap7sc7p5t_DFFHQNV2X.lef
+read_lib ./2BitTrayH2/asap7sc7p5t_DFFHQNV2X_LVT_TT_nldm_FAKE.lib
+
+read_lef ./4BitTrayH4/asap7sc7p5t_DFFHQNV4X.lef
+read_lib ./4BitTrayH4/asap7sc7p5t_DFFHQNV4X_LVT_TT_nldm_FAKE.lib
+
+read_lef ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X.lef
+read_lib ./4BitTrayH2W2/asap7sc7p5t_DFFHQNH2V2X_LVT_TT_nldm_FAKE.lib
+
+read_def ./$test_name.def
+
+create_clock -name clk -period 1000 [get_ports clk1]
+set_input_delay -clock clk 0 [get_ports {d1 d2 d3 d4}]
+
+cluster_flops -tray_weight 40.0 \
+  -timing_weight 1.0 \
+  -max_split_size -1 \
+  -num_paths 0
+
+# Report timing to verify original FF names appear in the path report.
+# After clustering the tray pin descriptions should show in the Orig Name column.
+report_checks -path_delay max -fields {orig_name} -through [get_pins _tray_size2_7/D1]