Develop/v1.1 - #12
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Reviewed commit: 164029107a
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Adding this golden file makes test_010 an active regression, but the Vivado path derives the top-level name from CPU_tb_wave.v and invokes xelab with CPU_tb_wave, while the file still declares module CPU_tb. Consequently, running the documented suite with --sim vivado fails to elaborate this test; rename either the module or the file so the runner selects an existing design unit.
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| - 32 addressable locations | ||
| - 8-bit data width | ||
| - asynchronous read | ||
| - synchronous write |
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Change this to synchronous read: Memory.v only updates data_out inside always @(posedge clk) when rd && !wr, so consumers do not receive a newly addressed value asynchronously. The current description can lead users extending the datapath or writing timing-sensitive tests to assume behavior the RTL does not provide.
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| | `test_002` | Memory-module verification | | ||
| | `test_003` | Instruction-register verification | | ||
| | `test_004` | Accumulator verification | | ||
| | `test_005` | ALU arithmetic and logical operations | | ||
| | `test_006` | Controller FSM verification | |
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Correct these mappings before directing users to select a test by name: test_002 contains AM_tb.v, test_003 contains ALU_tb.v, test_004 contains Controller_tb.v, and the later entries are similarly shifted (test_005 is IR, test_006 is AC, and test_007 is Memory). Following this table therefore runs the wrong verification target for most module-level tests.
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| ## License | ||
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| This project is released under the **MIT License**. See the `LICENSE` file for details. |
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Do not direct users to a nonexistent file: a repository-wide tree search of this commit contains no LICENSE or COPYING file, so the stated licensing terms cannot be inspected from the project and the README link is broken. Add the intended MIT license text or revise this section and the license badge accordingly.
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