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Remove last open read cache #13248

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ccb92fa
Remove last open read cache from documentation
JosiahWI Jun 8, 2026
b8b1551
Remove last open read cache
JosiahWI Jun 8, 2026
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9 changes: 2 additions & 7 deletions doc/admin-guide/monitoring/statistics/core/cache-volume.en.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -130,12 +130,7 @@ a configuration with only one cache volume: :literal:`0`.
.. ts:stat:: global proxy.process.cache.volume_0.ram_cache.misses integer
:type: counter

Accumulates the number of misses to the LRU RAM cache for this volume. Note that this count includes hits to the other memory caches, including the last open read and aggregation buffer caches, so it may not represent the total number of cache accesses that go to disk.

.. ts:stat:: global proxy.process.cache.volume_0.last_open_read.hits integer
:type: counter

Accumulates the number of hits to the last open read cache for this volume. This cache stores the most recent read operation for each open cache volume.
Accumulates the number of misses to the LRU RAM cache for this volume. Note that this count includes hits to the other memory caches, including the aggregation buffer caches, so it may not represent the total number of cache accesses that go to disk.

.. ts:stat:: global proxy.process.cache.volume_0.aggregation_buffer.hits integer
:type: counter
Expand All @@ -145,7 +140,7 @@ a configuration with only one cache volume: :literal:`0`.
.. ts:stat:: global proxy.process.cache.volume_0.all_memory_caches.misses integer
:type: counter

Accumulates the number of misses to all memory caches (LRU RAM cache, last open read cache, and aggregation buffer) for this volume. This represents the total number of cache accesses that go to disk for this volume.
Accumulates the number of misses to all memory caches (LRU RAM cache and aggregation buffer) for this volume. This represents the total number of cache accesses that go to disk for this volume.

.. ts:stat:: global proxy.process.cache.volume_0.ram_cache.total_bytes integer
:type: gauge
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9 changes: 2 additions & 7 deletions doc/admin-guide/monitoring/statistics/core/cache.en.rst
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Expand Up @@ -93,12 +93,7 @@ Cache
.. ts:stat:: global proxy.process.cache.ram_cache.misses integer
:type: counter

Accumulates the number of misses to the LRU RAM cache for all volumes. Note that this includes hits to the other memory caches, including the last open read and aggregation buffer caches, so it may not represent the total number of cache accesses that go to disk.

.. ts:stat:: global proxy.process.cache.last_open_read.hits integer
:type: counter

Accumulates the number of hits to the last open read cache for all volumes. This cache stores the most recent read operation for each open cache volume.
Accumulates the number of misses to the LRU RAM cache for all volumes. Note that this includes hits to the other memory caches, including the aggregation buffer caches, so it may not represent the total number of cache accesses that go to disk.

.. ts:stat:: global proxy.process.cache.aggregation_buffer.hits integer
:type: counter
Expand All @@ -108,7 +103,7 @@ Cache
.. ts:stat:: global proxy.process.cache.all_memory_caches.misses integer
:type: counter

Accumulates the number of misses to all memory caches (LRU RAM cache, last open read cache, and aggregation buffer) for all volumes. This represents the total number of cache accesses that go to disk.
Accumulates the number of misses to all memory caches (LRU RAM cache and aggregation buffer) for all volumes. This represents the total number of cache accesses that go to disk.

.. ts:stat:: global proxy.process.cache.ram_cache.total_bytes integer
.. ts:stat:: global proxy.process.cache.read.active integer
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1 change: 0 additions & 1 deletion src/iocore/cache/CacheProcessor.cc
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Expand Up @@ -1176,7 +1176,6 @@ register_cache_stats(CacheStatsBlock *rsb, const std::string &prefix)
rsb->ram_cache_bytes_total = ts::Metrics::Gauge::createPtr(prefix + ".ram_cache.total_bytes");
rsb->ram_cache_bytes = ts::Metrics::Gauge::createPtr(prefix + ".ram_cache.bytes_used");
rsb->ram_cache_hits = ts::Metrics::Counter::createPtr(prefix + ".ram_cache.hits");
rsb->last_open_read_hits = ts::Metrics::Counter::createPtr(prefix + ".last_open_read.hits");
rsb->agg_buffer_hits = ts::Metrics::Counter::createPtr(prefix + ".aggregation_buffer.hits");
rsb->ram_cache_misses = ts::Metrics::Counter::createPtr(prefix + ".ram_cache.misses");
rsb->all_mem_misses = ts::Metrics::Counter::createPtr(prefix + ".all_memory_caches.misses");
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34 changes: 2 additions & 32 deletions src/iocore/cache/CacheVC.cc
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Expand Up @@ -428,14 +428,6 @@ CacheVC::handleReadDone(int event, Event * /* e ATS_UNUSED */)
uint64_t o = dir_offset(&dir);
stripe->ram_cache->put(read_key, buf.get(), doc->len, http_copy_hdr, o);
}
if (!doc_len) {
// keep a pointer to it. In case the state machine decides to
// update this document, we don't have to read it back in memory
// again
stripe->first_fragment_key = *read_key;
stripe->first_fragment_offset = dir_offset(&dir);
stripe->first_fragment_data = buf;
}
} // end VIO::READ check
// If it could be compressed, unmarshal after
if (http_copy_hdr && doc->doc_type == CACHE_FRAG_TYPE_HTTP && doc->hlen && okay) {
Expand Down Expand Up @@ -473,17 +465,7 @@ CacheVC::handleRead(int /* event ATS_UNUSED */, Event * /* e ATS_UNUSED */)
return EVENT_RETURN;
}

// 2. check last open read cache
if (load_from_last_open_read_call()) {
Dbg(dbg_ctl_cache_ram, "last open read hit");
f.doc_from_ram_cache = true;
io.aio_result = io.aiocb.aio_nbytes;

POP_HANDLER;
return EVENT_RETURN;
}

// 3. check aggregation buffer
// 2. check aggregation buffer
if (load_from_aggregation_buffer()) {
Dbg(dbg_ctl_cache_ram, "aggregation buffer hit");
f.doc_from_ram_cache = true;
Expand All @@ -493,7 +475,7 @@ CacheVC::handleRead(int /* event ATS_UNUSED */, Event * /* e ATS_UNUSED */)
return EVENT_RETURN;
}

// 4. read from Disk (AIO) due to all memory cache miss
// 3. read from Disk (AIO) due to all memory cache miss
Dbg(dbg_ctl_cache_ram, "all memory cache miss");

ts::Metrics::Counter::increment(cache_rsb.all_mem_misses);
Expand Down Expand Up @@ -529,18 +511,6 @@ CacheVC::load_from_ram_cache()
return ram_hit_state >= RAM_HIT_COMPRESS_NONE;
}

bool
CacheVC::load_from_last_open_read_call()
{
if (*this->read_key == this->stripe->first_fragment_key && dir_offset(&this->dir) == this->stripe->first_fragment_offset) {
this->buf = this->stripe->first_fragment_data;
ts::Metrics::Counter::increment(cache_rsb.last_open_read_hits);
ts::Metrics::Counter::increment(stripe->cache_vol->vol_rsb.last_open_read_hits);
return true;
}
return false;
}

bool
CacheVC::load_from_aggregation_buffer()
{
Expand Down
1 change: 0 additions & 1 deletion src/iocore/cache/CacheVC.h
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Expand Up @@ -133,7 +133,6 @@ struct CacheVC : public CacheVConnection {
int handleReadDone(int event, Event *e);
int handleRead(int event, Event *e);
bool load_from_ram_cache();
bool load_from_last_open_read_call();
bool load_from_aggregation_buffer();
int do_read_call(CacheKey *akey);
int handleWrite(int event, Event *e);
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1 change: 0 additions & 1 deletion src/iocore/cache/P_CacheStats.h
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Expand Up @@ -45,7 +45,6 @@ struct CacheStatsBlock {
ts::Metrics::Gauge::AtomicType *direntries_total = nullptr;
ts::Metrics::Gauge::AtomicType *direntries_used = nullptr;
ts::Metrics::Counter::AtomicType *ram_cache_hits = nullptr;
ts::Metrics::Counter::AtomicType *last_open_read_hits = nullptr;
ts::Metrics::Counter::AtomicType *agg_buffer_hits = nullptr;
ts::Metrics::Counter::AtomicType *ram_cache_misses = nullptr;
ts::Metrics::Counter::AtomicType *all_mem_misses = nullptr;
Expand Down
4 changes: 0 additions & 4 deletions src/iocore/cache/StripeSM.h
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Expand Up @@ -144,10 +144,6 @@ class StripeSM : public Continuation, public Stripe
CacheSync *waiting_dir_sync = nullptr;
bool writing_end_marker = false;

CacheKey first_fragment_key;
int64_t first_fragment_offset = 0;
Ptr<IOBufferData> first_fragment_data;

void cancel_trigger();

int recover_data();
Expand Down