Rockchip: youyeetoo yy3568: enable pci-e NVMe ssd

[hqnicolas]

Description

This PR replaces #9832 , applying the changes requested by https://github.com/Arthur97172
I keep this dedication here in recognition of Arthur's effort.

To the author, we can close the PR.
#9832

Fixed NVMe SSD detection issue on Youyeetoo YY3568.

tested on 7.0.9-edge-rockchip64 by @hqnicolas
https://paste.armbian.com/amimofemog

tested on 6.18.32-current-rockchip64 by @hqnicolas
https://paste.armbian.com/ekupotacut

Problem

• PCIe PHY lock failed (rockchip_p3phy_rk3568_init: lock failed)
• M.2 NVMe SSD not detected (Phy link never came up)

Root Cause

Missing / incorrect configuration for:

• SSD 3.3V power enable (GPIO3_C3)
• PCIe Clock generator enable (GPIO3_A7, active low)
• REFCLK (100MHz) to PCIe3 PHY
• Wrong regulator polarity and missing startup delay

Solution

• Added correct pcie30_pwr and pcie_oe pinctrl
• Added proper regulators (vcc3v3_pcie + pcie_oe_regulator with active-low)
• Updated &combphy1, &pcie30phy and &pcie3x2 with correct clocks, phy-supply and reset polarity
• Added startup-delay-us for power stability

This makes the M.2 NVMe SSD work reliably on YY3568.

Documentation summary for feature / change

• Short description: Fixed NVMe SSD support on Youyeetoo YY3568
• Summary: YY3568 now correctly detects and uses M.2 NVMe SSDs (PCIe 3.0).

How Has This Been Tested?

• Test A: Booted 7.0.9-edge-rockchip64 on YY3568 with various NVMe SSDs (Samsung 970 EVO, WD SN770, etc.)
• Test B: Verified lspci shows NVMe device and lsblk / nvme list works
• Test C: Cold boot + warm reboot tested multiple times (stable)

Test Configuration:

• Board: Youyeetoo YY3568
• 6.18.32-current-rockchip64
• 7.0.9-edge-rockchip64

Checklist:

• My code follows the style guidelines of this project
• I have performed a self-review of my own code
• I have commented my code, particularly in hard-to-understand areas
• My changes generate no new warnings
• Any dependent changes have been merged and published in downstream modules

Summary by CodeRabbit

• New Features

  • Enabled audio interface support on the RK3568 YY3568 board.
  • Improved PCIe controller configuration and power management.
  • Enhanced Ethernet PHY and clock configuration.

• Bug Fixes

  • Adjusted power supply routing and regulator definitions for hardware stability.
  • Updated pinctrl configurations for peripheral control.

• Chores

  • Updated device tree configurations across kernel versions 6.18, 7.0, and 7.1, and u-boot.
  • Enabled storage interface support.

[coderabbitai]

Actionable comments posted: 2

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)

patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts (1)

220-221: ⚠️ Potential issue | 🟠 Major | ⚡ Quick win

pmic-reset never selects the reset mux.

pinctrl-3 points at &soc_slppin_gpio, while soc_slppin_rst is defined below and otherwise unused. That leaves the pmic-reset state in GPIO mode instead of RK_FUNC_2, so PMIC reset requests will not drive the intended reset function.

🛠️ Proposed fix

-		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
+		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;

Also applies to: 553-557

🤖 Prompt for AI Agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

In `@patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts` around lines
220 - 221, pinctrl-3 currently references &soc_slppin_gpio instead of the reset
mux, so the pmic-reset state remains in GPIO mode; update the device-tree
entries that define the pmic-reset pin state (pinctrl-3) to reference
&rk817_slppin_rst (which selects RK_FUNC_2) instead of &soc_slppin_gpio so PMIC
reset requests use the reset mux; apply the same correction to the duplicate
block around lines 553-557 where the same mistaken reference appears (look for
symbols pinctrl-3, &soc_slppin_gpio, &rk817_slppin_rst, and pmic-reset).

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts`:
- Around line 126-143: The &gmac0 node currently uses phy-mode = "rgmii" with
clock_in_out = "output" but does not specify controller-side RGMII delays;
update the &gmac0 device tree node to either add appropriate tx_delay and
rx_delay properties (e.g., tx_delay = <...>; rx_delay = <...>) so the dwmac
controller applies the timing, or change phy-mode to the correct
rgmii-id/rgmii-rxid/rgmii-txid variant that indicates the PHY handles delays;
modify the properties in the &gmac0 node (phy-mode, add tx_delay/rx_delay)
accordingly to match where delays are implemented.

---

Outside diff comments:
In `@patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts`:
- Around line 220-221: pinctrl-3 currently references &soc_slppin_gpio instead
of the reset mux, so the pmic-reset state remains in GPIO mode; update the
device-tree entries that define the pmic-reset pin state (pinctrl-3) to
reference &rk817_slppin_rst (which selects RK_FUNC_2) instead of
&soc_slppin_gpio so PMIC reset requests use the reset mux; apply the same
correction to the duplicate block around lines 553-557 where the same mistaken
reference appears (look for symbols pinctrl-3, &soc_slppin_gpio,
&rk817_slppin_rst, and pmic-reset).

🪄 Autofix (Beta)

Fix all unresolved CodeRabbit comments on this PR:

• Push a commit to this branch (recommended)
• Create a new PR with the fixes

---

ℹ️ Review info

⚙️ Run configuration

Configuration used: Path: .coderabbit.yaml

Review profile: CHILL

Plan: Pro

Run ID: c55526ae-aeeb-430d-87b4-ad1cd4bbfd36

📥 Commits

Reviewing files that changed from the base of the PR and between 869f0df and 9f4c226.

📒 Files selected for processing (4)

• patch/kernel/archive/rockchip64-6.18/dt/rk3568-yy3568.dts
• patch/kernel/archive/rockchip64-7.0/dt/rk3568-yy3568.dts
• patch/kernel/archive/rockchip64-7.1/dt/rk3568-yy3568.dts
• patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts

[github-actions]

✅ This PR has been reviewed and approved — all set for merge!