Add SysTick counter reset in Cortex-M ports#560
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The SysTick counter value (NVIC offset 0x18) is indeterminate after reset. Without clearing it prior to enabling the timer, the first tick interval becomes unpredictable.
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Tested on Cortex-M4 with gcc |
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Commit message needs to be corrected |
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The SysTick counter value (NVIC offset 0x18) is indeterminate after reset. Without clearing it prior to enabling the timer, the first tick interval becomes unpredictable.
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