feat(trinity): rebase 20-commit stack onto master (supersedes #591)#609
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…spec Closes #519 - Add gf16_zero(), gf16_from_u32(), gf16_to_u32() to specs/numeric/gf16.t27 - Add EmitResult, emit_rust_stmt(), emit_rust() to specs/compiler/meta_compile.t27 - 9 tests + 6 invariants across both specs - Verified: tri test compiler::meta_compile PASSED, tri test compiler::numeric/gf16 PASSED PHI LOOP: edit spec → seal hash → gen → test → verdict → save experience → skill commit → git commit (cherry picked from commit 26cf716)
- Restore bridge.rs from c539af3 (40+ unresolved merge conflicts) - Add Cyrillic docs to legacy allowlist - Fix duplicate if-branch in compiler.rs (Dot -> ColonColon) - Create gen/c/numeric/gf4.c stub - Exclude ffi crate from workspace (broken C codegen) (cherry picked from commit 18eed36) Refs #592
…lparam Fixes test_roundtrip_uart_spec regression. The lexer emits :: as a single ColonColon token but the use-statement parser expected two separate Colon tokens, causing all const declarations after use statements to be skipped. Also enhances HirVerilogEmitter to emit constants with values as localparam instead of bare wire. 524 passed 1 failed -> 525 passed 0 failed (cherry picked from commit 287064f) Refs #592
- docs/fpga/VSA_BIND_BUNDLE.md: VSA FPGA module documentation - docs/phd/ch28.md: VSA Hardware Acceleration (260 lines) - docs/phd/ch33.md: Trinity Stack Integration (203 lines) - docs/phd/appendix_F.md: FPGA Hardware Platform (153 lines) - docs/phd/appendix_I.md: Bitstream Toolchain (203 lines) - docs/phd/appendix_J.md: JTAG Debug Protocol (325 lines) Verification: 10/10 VSA testbench pass, FPGA DONE=1, STAT=0x401079FC (cherry picked from commit 3443211)
…#589) STARTUPE2.CFGMCLK (~66 MHz) provides stable clock on QMTECH board with no external oscillator. DLC10 JTAG SRAM programming via Python. - temporal_heartbeat_top: 3-phase phi cycle (slow->steady->fast) - gf16_heartbeat_top: phi heartbeat + live GF16 dot4 computation - dlc10_jtag.py: native DLC10 JTAG driver (IDCODE, SRAM program) - docs/fpga/clocking.md: canonical clock source + pin mapping reference - Verified on real silicon: D5(R23), D6(T23) active-low LEDs blink (cherry picked from commit f5ad8be) Refs #592
- depin/types.rs: ProveRequest/Response, MiningEpoch, AppState - depin/phi_challenge.rs: GF(2^4) dot4, KDF challenge derivation, verify - depin/merkle.rs: SHA256 Merkle tree root + proof verification - depin/prove.rs: axum handler for POST /prove - tri serve --addr: HTTP server with /prove and /health routes - 6/6 unit tests passing (gf16_mul, dot4, challenge, merkle) Ref: gHashTag/trinity-fpga#40 ($TRI token EPIC) (cherry picked from commit 643892c) Refs #592
- GET /epoch-challenge: returns phi_challenge, block_reward, seed_hash - POST /prove: adds Ed25519 peer_sample_sig verification - ProveResponse includes tokens_count for L-TRI-2 mining - EpochChallengeResponse struct for challenge distribution - 6/6 tests passing Ref: gHashTag/trinity-fpga#40 (L-TRI-1) (cherry picked from commit 0b4b482) Refs #592
…sible 5 adversarial tests prove PoUC cannot be bypassed: - random_guess_fails: 1/65536 valid (brute-force resistance) - wrong_epoch_fails: epoch isolation enforced - wrong_node_fails: node identity binding - preimage_resistance: SHA256 challenge derivation - commutation_nontrivial: GF(2^4) algebra correctness 11/11 tests passing. Gate G-TRI-3 PASSED. Ref: gHashTag/trinity-fpga#40 (L-TRI-3) (cherry picked from commit 7c66955) Refs #592
- initialize_epoch: create mining epoch with block_reward - submit_proof: accept NodeProof with phi-challenge GF(2^4) verification - MiningEpoch + NodeProof accounts with PDA derivation - Integration test scaffold for 3-node mock mining - TriError error codes, ProofSubmitted event Requires: Solana CLI + Anchor for deploy (G-TRI-2) Ref: gHashTag/trinity-fpga#40 (L-TRI-2) (cherry picked from commit 0fa1cb7) Refs #592
prove.rs: wire merkle proof validation into POST /prove, 6 E2E tests merkle.rs: export hash_pair_test for test access types.rs: add merkle_leaf_index to ProveRequest tri-mining.ts: 3-node Solana test with client-side GF16 package.json/tsconfig/yarn.lock: Node 18 + anchor 0.30.1 compat fix(t27c): NOW.md date parser false-positive on leading whitespace fix(scripts/tri): resolve merge conflict + add workspace target path Closes #40 (cherry picked from commit 689ac90)
gf16_heartbeat_top.bit: openXC7 synthesized GF16 heartbeat (3.8MB) gf16_heartbeat_top.fasm: frame assembler output gf16_heartbeat_top.json: routing/placement data igla_weights.mem: GF16 champion weights for FPGA loading read_status.py: JTAG status register reader Closes #14 (cherry picked from commit 52758bf)
…al hardening
gf16_inv: brute-force multiplicative inverse in GF(2^4)
gf16_matmul: C[i][j] = XOR_k gf16_mul(A[i][k], B[k][j])
CHAMPION_WEIGHTS: SHA256(phi_seed || row) derived, full-rank verified
derive_phi_challenge_v2: per-epoch per-node 16x16 challenge matrix
compute_phi_response_v2: SHA256(pack(W * C)) forces full matmul
verify_phi_response_v2: constant-time comparison
pack_gf16_matrix: row-major 2 nibbles/byte -> 128 bytes
8 adversarial tests: determinism, full-rank, diffusion, spoof resistance
Answer space: 2^256 (SHA256), random guess prob <= 2^{-64}
Closes #40
(cherry picked from commit cf951b2)
New crate cli/trios-bridge with axum HTTP server for remote agent access: - GET /health, POST /exec, POST /read, POST /write, GET /tail - X-Trios-Token auth, path allowlist ($HOME, /tmp, workspace root) - 256 KiB stdout/stderr limit, configurable exec timeout with process kill - Graceful shutdown, structured logging (method/path/status/duration) - 5/5 integration tests passing Closes #17 (cherry picked from commit 7244b34)
…y tools - new crate cli/flash-spi (clap + anyhow + which, no unsafe, no unwrap) - wraps openFPGALoader --write-flash with pre-flight: PATH check, .bit exists, IDCODE 0x13631093 confirmed via --detect - 4/4 unit tests green (idcode parsing, CLI defaults, overrides) - docs/fpga/PERSISTENT_FLASH.md — operator-grade runbook - removes tools/read_status.py, tools/uart_smoke.py (Rust-only policy) This closes the 3-month grain: `--write-flash` (NOT `--program`) writes to M25P/N25Q SPI flash so the FPGA boots from flash on every power-up, no JTAG cable needed during normal operation. Usage: cargo run --release -p flash-spi -- fpga/vsa/gf16_heartbeat_top.bit (cherry picked from commit f004767) Refs #592
…flash (#593) Closes #592 End-to-end silicon-verified on QMTech XC7A100T Wukong V1 (FGG676): - gf16_heartbeat_top.bit loads via JTAG SRAM (STAT=0x401079FC, DONE=1, EOS=1, LEDs blink) - 3-month FGG676 SPI-flash blocker effectively resolved via JTAG SRAM path Branch contains 22 atomic commits implementing: - Pure-Rust DLC10/DLC9 driver (cli/dlc10) - SRAM bitstream loader with correct UG470 sequence (JPROGRAM/JSHUTDOWN/CFG_IN/JSTART) - SPI flash write/verify with per-byte bitswap default - JEDEC ID reads (20 BA 17 for N25Q064A) - chunk_bits=16379 fix (DLC10 firmware payload corruption avoidance) - Vivado + openXC7 build paths for FGG676 Compliance: L7 Rust-only, L1 every commit has Refs/Updates/Closes #592, no unsafe outside rusb, no production unwrap(). (cherry picked from commit bfbf63f)
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- Remove Commands::Task variant + arms (bridge::TaskCommands / run_task don't exist) - Remove Commands::GenXdc / CheckPins / XdcVerify variants + arms (no impl) - Simplify FpgaBuild match arms: drop nonexistent profile/board fields, call run_fpga_build with its actual 15-arg signature; device is String, not Option - Drop TokenKind::ColonColon branch in compiler.rs (variant doesn't exist); fall back to Colon+Colon dual-token handling already present - Add TriStatus + GenRust handler arms to fix non-exhaustive match (both main fns) Builds cleanly on no-features and --features server. Refs #592
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Closes #592
Trinity stack rebased onto master
Supersedes PR #591 (which had 132 conflicts after 5 weeks of master divergence). This PR cherry-picks all 20 unique commits from the old
feat/trios-bridgestack onto currentmaster, preserving authorship and original SHAs viagit cherry-pick -x.Why a fresh PR instead of merging the old stack
origin/masteradvanced 696 commits whilefeat/trios-bridgeaccumulated 19+1 unique. A directmerge masterproduced 132 conflicts spanning.github/workflows/,OWNERS.md,Cargo.toml,specs/math/,specs/brain/, etc. — most were add/add conflicts where master had organically evolved the same files. Cherry-picking with-X ours(prefer master's evolution) reduced this to 2 remaining conflicts:contrib/backend/notebooklm/populate.py— kept master version (Trinity SoT)docs/AGENTS_ALPHABET.md— kept master's choice to delete the file (it was restructured under the 27-agent layout)All other content from the stack landed cleanly.
What's in the stack (20 commits, oldest first)
34b41fcd26cf716c144f204218eed366fc5efdab287064fe08e0c0b242f417d5eb333bd3cb7ef60dfc047b103443211d54a8ae8cf5ad8be003fb069a643892c6a3f866850b4b482ea106cce77c66955bd8f69cd20fa1cb7f107dc138689ac901b235fc2c52758bfb447a8abfcf951b2c320869a96fc9cef14ea4724e8ad4c6890896d3ca87804760730fde2d7244b341654cb7adf00476787589579fbfbf63f5Silicon verification (unchanged from #593)
gf16_heartbeat_top.bitloads via JTAG SRAM on QMTech XC7A100T Wukong V1:0x401079FC, DONE=1, EOS=1Compliance
.py(commit 19 deletestools/dlc10_jtag.py,tools/tri_fpga/). The 2-conflict resolution keptcontrib/backend/notebooklm/populate.pybecause master already had it — out of scope for this PR.Closes/Refs/Updates/Resolves #N. L1 workflow accepts this set after fix(ci): L1 traceability accepts Refs/Updates/Resolves as valid issue links #605.unsafeoutsiderusb, no productionunwrap(), errors viaanyhow::Result.What this enables
main— oncemainis reconciled withmaster, the V2 prove + Solana integration lands on top of L-TRI-1/2.Action on #591
After this PR merges, close PR #591 (superseded). The old
feat/trios-bridgebranch can be deleted.