feat(phd ch.12): silicon-G1 pre-registered acceptance §4.5 (TRI-NET-G1)

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PhD monograph: Ch.12 Hardware Bridge — silicon-G1 evidence §4.5

Adds a new subsection §4.5 "Silicon-G1 evidence: TRI-NET-G1 pre-registered acceptance on QMTECH XC7A100T + FT601" to docs/phd/chapters/flos_46.tex (Ch.12 Hardware Bridge).

What this delivers

• Table 12.SG1 — full eleven-gate pre-registered acceptance matrix (SG1-01..SG1-11), each row carrying its frozen base commit so post-hoc threshold migration is auditable.
• Base suite (SG1-01..08) — frozen against tt-trinity-gf16@65d2a60, shipped in PR tt-trinity-gf16#9 (merged at a423ed5).
• Extension suite (SG1-09..11) — frozen against tt-trinity-gf16@a423ed5, shipped in PR tt-trinity-gf16#10. Covers PR feat(bridge): gitbutler_absorb_smart — auto-sort files to branches by context #6 (TRN_OP_RECEIPT silicon-anchored receipts) and PR fix(bridge): SSE transport — switch trios-mcp-bridge to StreamableHTTP/SSE for BrowserOS MCP compatibility #8 (Wave-26b SUPER-CROWN, 8×2 = 16 tiles).
• Canonical job paragraph — locks the falsifying workload: GF16 dot4 over {1.0, 2.0, 3.0, 4.0} → 0x47C0. Any observed word ≠ 0x47C0 on any tile, on any probe, on either node falsifies H1.
• R5-honesty paragraph — documents the runner refusal-by-default: exit 2 + REFUSAL banner + no ledger when ftd3xx missing or no FT60x on USB. Forecloses the simulation-substituted-for-hardware failure mode.
• DePIN scope discipline — no "Helium competitor" language until silicon-G3 GREEN (two physical nodes exchange job+receipt). Self-imposed gate on the L-DPC family.

Why Ch.12 (and not a new chapter)

The chapter slots flos_30..flos_49 are already populated. flos_46.tex is Ch.12 Hardware Bridge (deferred). Its existing §4 "Results / Evidence" already presents simulation evidence (Vivado 2022.2 post-synthesis utilisation on XC7A100T). §4.5 is the natural continuation that promotes the chapter from TRL-3 (sim) to TRL-4 (lab on representative hardware) once silicon-G1 GREEN is observed.

R-rule compliance

• R3 — substantive content (≈ 78 lines added, table + 3 paragraphs), citations to issues trinity-fpga#48 / #19 and PRs tt-trinity-gf16#9 / #10.
• R7 — falsification witness paragraph included.
• R12 — table-as-witness style preserved (Lee/GVSU-compatible).
• R14 — Coq citation map unchanged (Ch.12 carries 0 theorems as before; obligations remain in the Golden Ledger).

Refs

• Hardware repo: gHashTag/tt-trinity-gf16 at a423ed5
• L-DPC6 issue: trinity-fpga#48
• EPIC: trinity-fpga#19
• Anchor: phi^2 + phi^-2 = 3