Netlist by desmonddak · Pull Request #675 · intel/rohd

desmonddak · 2026-07-02T23:59:59Z

Description & Motivation

This is a netlist synthesizer that produces a netlist for the generated design in an extension of the Yosys output netlist format.
It provides routines for emitting just the hierarchy and ports ("slim" mode) as well as fully expanded and has hooks for even more incremental expansion modes.

Related Issue(s)

None.

Testing

There is a suite of tests that compare the netlist and its names against the SystemVerilog output. This netlist depended on the last central_naming branch to assure that signals in both formats had identical names.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No.

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

This is a minor API addition (Module.generateNetlist()) but we will add more documentation and examples of the format, etc.
It will have some options as well, such as multiFile, which should parallel the generateSynth() API.

…agree on names

…al/instance naming routine names

Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>

This aligns central_naming with the simplified naming approach already adopted by all downstream branches (module_services, netlist, source_debug, systemc_trace, fst-writer). Changes: - Remove Namer._instanceNames cache field - Remove Namer.instanceNameOf(Module) method - Update synthesizers to use Namer.allocateName(String) directly - Remove destination tracking from _BusSubsetForStructSlice Benefit: Eliminates duplication across 5+ branches, making each branch truly orthogonal and mergeable without conflicts. Trade-off: Instance names no longer cached across synthesis passes, but all downstreams already use this simpler approach.

…ning

# Conflicts: # tool/gh_codespaces/install_dart.sh

instanceNameOf(Module) allocates a collision-free instance name on the first call and returns the cached result thereafter. The _instanceNames Map is keyed by Module.instanceNameKey so repeated synthesis passes over the same hierarchy always produce stable names. This method belongs in central_naming because it is pure naming infrastructure with no dependency on any feature branch.

- Update comment: 'allocateName' → 'instanceNameOf' - Add 'submodule instance names are stable across repeated definitions' test (the canonical 'run synthesis twice, same names' regression test) Both belong here since they directly exercise Namer.instanceNameOf, which is now defined in central_naming.

mkorbel1

can you pull main also again just so it's up to date?

mkorbel1 · 2026-08-10T21:12:31Z

+  ///
+  /// This is backward-compatible: Yosys-format arrays already mix
+  /// integers with constant strings `"0"` and `"1"`.  Parsers can
+  /// detect range strings by the presence of `:`.


why do you want this to be exposed as a configurability option? any config you have is something you have to support or else deprecate in the future. this applies to the other ones in here too (e.g. enableDCE)

I made these internal only for now in tests. The reason is that we really should study migrating these optimizations into the core synthesis traversal.

I still see compressBitRanges as non-internal, is that intentional?

Made internal

mkorbel1 · 2026-08-17T19:59:17Z

+
+import 'package:rohd/rohd.dart';
+
+/// Provides bit ranges and field names for a packed [LogicStructure].


question: this applies to the leaves of a structure if there is hierarchy?

It recurses: _addStructure line 46

if (element is LogicStructure && element is! LogicArray) { _addStructure(element, offset, path); }

but i mean if you ask for a.b.c vs a.b it can give you either one?

Yes. It gives you the range of bits for whatever field you choose regardless of what level of hierarchy.
I added a method that will export this range.

test('returns bit ranges for nested field paths', () { final nested = LogicStructure([ Logic(name: 'b', width: 2), LogicStructure([ Logic(name: 'd', width: 3), ], name: 'c'), ], name: 'a'); final structure = LogicStructure([ Logic(name: 'prefix'), nested, ]); final layout = SynthStructureLayout(structure); expect(layout.bitRangeForPath('a'), (start: 1, end: 6)); expect(layout.bitRangeForPath('a.b'), (start: 1, end: 3)); expect(layout.bitRangeForPath('a.c'), (start: 3, end: 6)); expect(layout.bitRangeForPath('a.c.d'), (start: 3, end: 6)); expect(layout.bitRangeForPath('a.missing'), isNull); });

mkorbel1 · 2026-08-17T20:01:36Z

  String get instanceTypeName => getInstanceTypeOfModule(module);

+  /// Non-fatal warnings reported while producing this synthesis result.
+  final List<String> warnings;


In general, been avoiding adding "warnings" to ROHD -- either things are bad and fatal or good and allowed. Trying to avoid warning soup that happens in a lot of EDA flows, where they grow forever to the point where it's just slowing down and bloating logs. Do we really need warnings?

I removed the warnings, and use a throw instead.

I still see warnings APIs added to synthesis result etc.

I removed the dead plumbing for collecting ...

Moved from Options to Configuration nomenclature. Dependency on rohd_hierarchy so we can use Occurrence classes Leverage Namer and eliminate residual naming functionality. Remove warnings and move to just throw on error.

Copilot

Pull request overview

Adds a Yosys-style JSON netlist synthesizer, shared synthesis utilities, hierarchy support, and a filter-bank example.

Changes:

Introduces configurable netlist generation, validation, cell mapping, and optimization passes.
Adds shared array/structure synthesis utilities and warning propagation.
Adds extensive netlist tests and hierarchical filter-bank examples.

Reviewed changes

Copilot reviewed 41 out of 41 changed files in this pull request and generated 10 comments.

Show a summary per file

File	Description
`test/synth_structure_layout_test.dart`	Tests packed structure layout.
`test/synth_name_parity_test.dart`	Tests naming parity across synthesizers.
`test/struct_port_pruning_test.dart`	Tests structured-port preservation.
`test/netlist_test.dart`	Tests netlist APIs and JSON output.
`test/netlist_example_test.dart`	Tests example netlist generation.
`pubspec.yaml`	Adds hierarchy dependency and publication settings.
`lib/src/synthesizers/utilities/utilities.dart`	Exports new synthesis utilities.
`lib/src/synthesizers/utilities/synth_structure_slice.dart`	Adds structure-slice helper.
`lib/src/synthesizers/utilities/synth_structure_layout.dart`	Adds structure layout mapping.
`lib/src/synthesizers/utilities/synth_structure_concat.dart`	Adds structure concatenation helper.
`lib/src/synthesizers/utilities/synth_module_stop_policy.dart`	Adds hierarchy stopping policies.
`lib/src/synthesizers/utilities/synth_logic.dart`	Adds nullable synthesized-name access.
`lib/src/synthesizers/utilities/synth_array_slice.dart`	Adds array-slice helper.
`lib/src/synthesizers/utilities/synth_array_concat.dart`	Adds array concatenation helper.
`lib/src/synthesizers/synthesizers.dart`	Exports netlist APIs.
`lib/src/synthesizers/synthesis_result.dart`	Adds synthesis warnings.
`lib/src/synthesizers/synth_builder.dart`	Aggregates result warnings.
`lib/src/synthesizers/netlist/netlist.dart`	Adds netlist barrel exports.
`lib/src/synthesizers/netlist/netlist_validation.dart`	Validates generated connectivity.
`lib/src/synthesizers/netlist/netlist_utils.dart`	Adds netlist translation utilities.
`lib/src/synthesizers/netlist/netlist_synthesizer.dart`	Implements JSON netlist synthesis.
`lib/src/synthesizers/netlist/netlist_synthesizer_configuration.dart`	Defines netlist options.
`lib/src/synthesizers/netlist/netlist_synthesis_result.dart`	Stores per-module netlists.
`lib/src/synthesizers/netlist/netlist_synth_module_definition.dart`	Preserves structural netlist cells.
`lib/src/synthesizers/netlist/netlist_passes.dart`	Adds optimization passes.
`lib/src/synthesizers/netlist/netlist_module_translation.dart`	Translates modules into netlist data.
`lib/src/synthesizers/netlist/netlist_cell_mapper.dart`	Maps ROHD modules to cells.
`lib/src/signals/const.dart`	Reformats constant construction.
`lib/src/module.dart`	Refactors constant detection.
`example/filter_bank/shared_data_bus.dart`	Adds bidirectional-bus example.
`example/filter_bank/mac_unit.dart`	Adds pipelined MAC example.
`example/filter_bank/filter_sample.dart`	Adds structured sample type.
`example/filter_bank/filter_data_interface.dart`	Adds filter interface.
`example/filter_bank/filter_controller.dart`	Adds filter FSM controller.
`example/filter_bank/filter_channel.dart`	Adds FIR channel implementation.
`example/filter_bank/filter_bank.dart`	Adds filter-bank top module.
`example/filter_bank/filter_bank_modules.dart`	Exports filter modules.
`example/filter_bank/coeff_bank.dart`	Adds coefficient storage.
`example/filter_bank.dart`	Adds simulation entry point.
`dart_test.yaml`	Configures benchmark timeout.

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+        return (
+          cellType: r'$dff',
+          portDirs: pd,
+          connections: cn,
+          parameters: <String, Object?>{
+            'WIDTH': ctx.width(d),
+            'CLK_POLARITY': 1,
+          },


+        const <Type, String>{
+          LShift: r'$shl',
+          RShift: r'$shr',
+          ARShift: r'$shiftx',


+      final inName = tsb.inputs.keys.first; // data input
+      final enName = tsb.inputs.keys.last; // enable
+      final outName = tsb.inOuts.keys.first; // inout output
+      final r = ctx.remap({inName: 'A', enName: 'EN', outName: 'Y'});


desmonddak · 2026-08-20T21:05:12Z

+extension _NetlistTestModule on Module {
+  String generateNetlist(


This is correct. We will not be adding to the Module API for new services, we will use the service model. Only for SV and Waves do we have these generate routines. This is as agreed, right -- the helper routines are for simplifying the most common two cases.

+  final parts = [
+    ..._modulePathIndices(module).path,
+    ...rootLocation.path,
+    ...elementPath,


+    final pipe = Pipeline(
+      clk,
+      reset: reset,
+      stages: [


 repository: https://github.com/intel/rohd
 issue_tracker: https://github.com/intel/rohd/issues
 documentation: https://intel.github.io/rohd-website/docs/sample-example/
+publish_to: none


+    if (coefficients.length != numChannels) {
+      throw Exception(
+          'coefficients must have $numChannels entries (one per channel).');
+    }


+
+/// A structured signal bundling a data sample with metadata.
+///
+/// Packs three fields — [data], and [valid] — into a single


+        if (carryName.isNotEmpty) {
+          pd['CO'] = 'output';
+          cn['CO'] = ctx.rawConns[carryName] ?? [];
+        }


mkorbel1 · 2026-08-20T16:12:03Z

+  ///
+  /// This is backward-compatible: Yosys-format arrays already mix
+  /// integers with constant strings `"0"` and `"1"`.  Parsers can
+  /// detect range strings by the presence of `:`.


I still see compressBitRanges as non-internal, is that intentional?

mkorbel1 · 2026-08-20T16:24:08Z

+
+      for (final cellEntry in cells.entries) {
+        if (!cellEntry.key.startsWith(
+          SynthArraySlice.operationName,


is a string "starts with" really a robust method for identifying the type of a module?

compressBitRanges?

mkorbel1 · 2026-08-20T17:21:00Z

  String get instanceTypeName => getInstanceTypeOfModule(module);

+  /// Non-fatal warnings reported while producing this synthesis result.
+  final List<String> warnings;


I still see warnings APIs added to synthesis result etc.

mkorbel1 · 2026-08-20T17:26:41Z

+  int nextId = 2;
+
+  /// Wire identifiers allocated for each synthesis logic.
+  final Map<SynthLogic, List<int>> synthLogicIds = {};


i notice this synthLogicIds, blockedConstSynthLogics, are not referenced outside of this class. even though it's an internal class, might be worth considering which pieces should be private to prevent leaky abstractions?

mkorbel1 · 2026-08-20T17:28:54Z

+    concatConnections['Y'] = outputIds.cast<Object>();
+    concatDirections['Y'] = 'output';
+
+    cells['array_concat_output_$concatName'] = {


is this guaranteed unique? does it have to be?

mkorbel1 · 2026-08-20T17:46:51Z

+  /// and be emitted as cells in their parent. Defaults to [FlipFlop], which
+  /// contains internal sequential submodules but should be emitted as a `$dff`
+  /// netlist cell.
+  final List<Type> leafModuleTypes;


should this be private with an UnmodifiableListView accessor (if needed)?

mkorbel1 · 2026-08-20T17:49:31Z

+  /// [leafModuleTypes] is ignored.
+  final SynthModuleStopPolicy? moduleStopPolicy;
+
+  /// Exact [Module.runtimeType]s that should stop netlist hierarchy traversal


runtimeType is maybe a little too delicate? First, it's sort of weird when you compile to javascript with optimization. Second, it means it doesn't handle inheritance gracefully (e.g. if someone makes a custom version that extends FlipFlop they need to remember to update this policy too). Would a Function be better with a default that checks is FlipFlop be better?

mkorbel1 · 2026-08-20T18:16:53Z

    return outPort;
  }

+  bool _hasConsts(LogicStructure structure) => structure.elements.any(


why did you change this from the private extension on LogicStructure to a method on Module?

mkorbel1 · 2026-08-20T18:18:47Z

+// SPDX-License-Identifier: BSD-3-Clause
+//
+// synth_name_parity_test.dart
+// Tests that verify canonicalNameOf works consistently across


there's no more canonicalNameOf?

mkorbel1 · 2026-08-20T18:20:05Z

 repository: https://github.com/intel/rohd
 issue_tracker: https://github.com/intel/rohd/issues
 documentation: https://intel.github.io/rohd-website/docs/sample-example/
+publish_to: none


no :) we do want to publish rohd

is it complaining that the path dependency is not allowed if we publish? what's the right way to handle this then? do we need to release rohd_hierarchy also?

We want to be able to use the local version when we are in this repo. I will try to figure this out, but it is the monorepo problem with multiple packages. You don't want to be in a loop where you have to publish to test a change that crosses between the package and the rest of the repo. But it complained about using a path for an internal package.

WE do need to release rohd_hierarchy in pub.dev. Perhaps this is a dependency override situation.

https://dart.dev/tools/pub/workspaces

desmonddak and others added 30 commits April 17, 2026 08:30

move synthesis naming to a common naming utility so all synthesizers …

82e900e

…agree on names

dart 3.11 parameter_assignments pickiness

85f88ce

Merge branch 'main' into central_naming

b1de1e5

conflict resolved and dart format . works

b7087c4

properly assign naming spaces for instances vs signals

4a55214

format issue

ed7be36

Controllable enforcement of signal vs instance name uniqueness.

ab09aed

Refactored to Namer class. No external API changes for ROHD

520d280

signal registry

61d0319

module context name uniquification instead of signal/instance split

becdb36

Merge branch 'main' into central_naming

a86f80c

cleanup of port vs signal name assumptions, constant merging and sign…

d5904a6

…al/instance naming routine names

simplified forModule, improved code doc

6dfe0f9

more coverage for Namer

3c90e5d

canonical names at last, even in the comments

42fba62

pesky override rule surfaced again on tutorials file

6a41f8d

new keyring-based installation for dart in codespaces

139280f

new keyring-based installation for dart in codespaces

62e4a2c

keyring-style dart installation rather than holding keys

caecb02

new dart analyzer failure with bad override

089faf8

Merge branch 'override-bug' into new-dart

e015889

Potential fix for pull request finding

1232afb

Clarify comment Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>

Fix orthogonalized Namer: remove stale instanceNameOf method

8ef6820

Clean DevTools extension analysis and formatting

1225df1

Keep DevTools extension changes on owning branches

c8440c4

added back pubkeys, and made a wget a fallback solution with loud war…

a87fa5c

…ning

Merge branch 'new-dart' into central_naming

d2760eb

# Conflicts: # tool/gh_codespaces/install_dart.sh

Move filter bank example modules out of lib

8c48a81

mkorbel1 reviewed Jul 13, 2026

View reviewed changes

desmonddak added 5 commits July 15, 2026 08:22

major bug fixes for LogicArray and LogicStruct

1c7cd05

conflict resolved, sv_gen test fix

cbda4eb

inout fix

57fc237

attempt with better VS links

5a8a25f

bump copyright

8ac1936

mkorbel1 reviewed Jul 22, 2026

View reviewed changes

desmonddak added 5 commits July 24, 2026 07:53

major cleanup from PR comments -- complete at this point

2001f47

much better testing of netlist passes

d43f406

Merge branch 'main' into netlist_pre

ded32ed

false positive on validation fixed

5f7999a

handle inouts properly

1cb81d9

desmonddak requested a review from mkorbel1 August 8, 2026 22:48

mkorbel1 reviewed Aug 17, 2026

View reviewed changes

desmonddak added 6 commits August 18, 2026 14:20

Merge remote-tracking branch 'origin/main' into netlist_pre

cbc2b2a

Hid generateNetlist until we have services available.

9f0081b

Moved from Options to Configuration nomenclature. Dependency on rohd_hierarchy so we can use Occurrence classes Leverage Namer and eliminate residual naming functionality. Remove warnings and move to just throw on error.

point to local rohd_hierarchy package, not pub

3721610

use publish_to: none for local package

39c6a84

Merge remote-tracking branch 'origin/main' into netlist_pre

0fc4cc9

Merge remote-tracking branch 'upstream/main' into netlist_pre

5045b93

desmonddak requested a review from mkorbel1 August 20, 2026 06:40

compressBitRanges is an optimization test feature

043837d

mkorbel1 requested a balanced review from Copilot August 20, 2026 17:29

Copilot AI reviewed Aug 20, 2026

View reviewed changes

mkorbel1 reviewed Aug 20, 2026

View reviewed changes

Copilot started reviewing on behalf of mkorbel1 August 20, 2026 20:51 View session

desmonddak added 3 commits August 20, 2026 16:54

fixes for full gate library, synth cell naming

8a1a1ed

fix authorship

2a2f614

gate catalog can be vm only

a195eac


		import 'package:rohd/rohd.dart';

		/// Provides bit ranges and field names for a packed [LogicStructure].

		extension _NetlistTestModule on Module {
		String generateNetlist(

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desmonddak commented Jul 2, 2026

Description & Motivation

Related Issue(s)

Testing

Backwards-compatibility

Documentation

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Pull request overview

Reviewed changes

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