[AMDGPU] Documentation files for GFX940#186924
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@llvm/pr-subscribers-backend-amdgpu Author: Jun Wang (jwanggit86) ChangesChecking in documentation files for GFX940. Patch is 1001.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/186924.diff 107 Files Affected:
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
index 7603bcc95383b..4b438d6c99018 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX940.rst
@@ -6,7 +6,7 @@
**************************************************
====================================================================================
-Syntax of gfx942 Instructions
+Syntax of GFX940 Instructions
====================================================================================
.. contents::
@@ -15,7 +15,7 @@ Syntax of gfx942 Instructions
Introduction
============
-This document describes the syntax of gfx942 instructions.
+This document describes the syntax of GFX940 instructions.
Notation
========
@@ -36,481 +36,636 @@ DS
.. parsed-literal::
- **INSTRUCTION** **DST** **SRC0** **SRC1** **SRC2** **MODIFIERS**
- \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- ds_add_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_add_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_and_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_append :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_bpermute_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>`
- ds_cmpst_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_cmpst_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_condxchg32_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_consume :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_dec_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_barrier :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_init :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_br :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_p :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_release_all :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_gws_sema_v :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_inc_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_i64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_i64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_max_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_f64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_i64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_f64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_i64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_rtn_u64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_min_u64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_be4895>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_mskor_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata0<amdgpu_synid_gfx940_vdata0_9ad749>`, :ref:`vdata1<amdgpu_synid_gfx940_vdata1_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_nop
- ds_or_b32 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_b64 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_or_rtn_b64 :ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_permute_b32 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>`
- ds_pk_add_bf16 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_pk_add_f16 :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_pk_add_rtn_bf16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
- ds_pk_add_rtn_f16 :ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vd...
[truncated]
|
shiltian
approved these changes
Mar 17, 2026
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Checking in documentation files for GFX940.