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PSU_ECE_RISC-V_ISA_Sim

Simple RISC-V ISA Simulator; ECE 486/586 Winter 2025 Final Project

Test Plan Document

To build use:

make main

Compile time argument flags.

-DVERBOSE -- Enable verbose output.
-DSTEP -- Enable key press instruction stepping.
-DDEBUG -- Enable debug output and define VEBOSE

Example:

$ make main EXTRA_CFLAGS="-DSTEP -DDEBUG"

Run time argument flags.
Default values are assumed when argument is absent.

-f <input file path> 
-s <stack Address> -- Starting stack address(Default = 65535)
-a <starting address> -- Word address(Default = 0)

Example:

$ ./main -f ./test_input.dat

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Simple RISC-V ISA Simulator; ECE 486/586 Winter 2025 Final Project

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