GitHub - pyrostrength/RISCV-OOO-CORE: RISCV Out-Of-Order CPU Core

RISC-V OOO Core implementing RV32I ISA. Targeting Basys3 board

Has: -Gshare branch predictor and branch target buffer -Hardware support for misaligned loads and stores thru multicylce operations

In Progress: -Speculative load store execution with load store forwarding -Exception handling -Superscalar operation -Linux Capable

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
RISCV.cache		RISCV.cache
RISCV.gen/sources_1/ip/clk_wiz_0		RISCV.gen/sources_1/ip/clk_wiz_0
RISCV.hw		RISCV.hw
RISCV.ip_user_files		RISCV.ip_user_files
RISCV.runs		RISCV.runs
RISCV.sim/sim_1		RISCV.sim/sim_1
RISCV.srcs		RISCV.srcs
impl_1		impl_1
synth_1		synth_1
README.md		README.md
RISCV.xpr		RISCV.xpr
instr.txt		instr.txt
pipeline_reset_tb_func_synth.wcfg		pipeline_reset_tb_func_synth.wcfg
reg_status_tb_func_synth.wcfg		reg_status_tb_func_synth.wcfg
ri_rs_tb_func_synth.wcfg		ri_rs_tb_func_synth.wcfg

Provide feedback