Cadence Xtensa OSS CI: gflags-free ISS runner + cross-compile build workflow#20205
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/20205
Note: Links to docs will display an error until the docs builds have been completed. ❌ 1 New Failure, 263 PendingAs of commit 3fef334 with merge base 193574d ( NEW FAILURE - The following job has failed:
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The upstream executor_runner cannot cross-compile to Xtensa because gflags pulls
in mkdir(2), absent from Xtensa newlib. Add cadence_executor_runner, a
gflags-free ExecuTorch runner for the Cadence Xtensa cores targeting the
Instruction Set Simulator (xt-run): it uses plain argv parsing like the Arm and
NXP backends, loads a .pte via xt-run semi-hosting, runs the first method with
all-ones inputs, and prints outputs. EXECUTORCH_BUILD_CADENCE_RUNNER builds it,
linking cadence_ops_lib transitively (no --whole-archive, which would double-run
static kernel registration); -lidma is linked only for Vision/Fusion-G3 cores,
whose ops reference iDMA and whose LSPs ship libidma, while HiFi4 does not. Also
register op_quantized_depthwise_conv1d_{ncl,nlc}.cpp in the HiFi4 operators
CMakeLists, which codegen references (omitting the sources broke the
cross-compile link).
Add an xtensa-build job to the Cadence Build & Test workflow
(build-cadence-runner.yml), alongside the existing host cpu-build/cpu-test, to
cross-compile the backend for the Xtensa cores. It is a build stage producing a
runner artifact; the ISS test stage follows separately (cf. cpu-build ->
cpu-test). The Xtensa toolchain and core configs are licensed and fetched at
runtime from an auth-gated object store via a short-lived OIDC credential; the
store, role, and region are provided through CI variables and are not committed.
Fork PRs are skipped because they cannot mint the OIDC token to assume the role.
setup-xtensa-tools.sh downloads and installs the toolchain/core for a backend,
rewrites the vendor params to local paths, and exports the Xtensa env;
build-cadence-xtensa.sh cross-compiles cadence_executor_runner. The job builds a
[hifi4, vision] matrix and uploads the runner.
fusion_g3 is omitted from the matrix until the upstream fusion_g3 <-> nnlib API
skew is fixed (its runner does not link).
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Superseded by #20208. Moved to an upstream same-repo branch so the Cadence Xtensa CI runs pre-merge instead of being skipped on fork PRs. Same single commit. |
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Summary
Adds OSS CI to cross-compile and run the Cadence (Xtensa) backend, so backend changes can be validated in CI rather than only through internal flows.
Two commits, review in order:
gflags-free ISS runner — the upstream
executor_runnercan't cross-compile to Xtensa (gflags pulls inmkdir(2), absent from Xtensa newlib). Adds a small argv-only runner (same approach as the Arm/NXP backends) that loads a.pteand runs it on the simulator. Also registers thequantized_depthwise_conv1dops the HiFi4 codegen references but the operators CMake omitted (broke the link).Xtensa cross-compile CI (build stage) — mirrors the host cadence CI in
build-cadence-runner.yml(build stage now; ISS test stage to follow, cf.cpu-build→cpu-test). The licensed toolchain/core artifacts are fetched at runtime from an auth-gated store via a short-lived OIDC credential; store/role/region/approval-environment are supplied through CI variables and are not committed. PR runs are gated behind an approval environment; fork PRs are skipped.Matrix covers
hifi4andvision.fusion_g3is omitted until an upstream operator/nnlib API skew is resolved (its runner does not link yet).Test plan
Validated locally end to end: setup + cross-compile produce an Xtensa ELF runner for
vision; the HiFi4 op sweep passes 15/15 on the simulator and a trivial model returns the expected output.cc @mcremon-meta