FROMLIST: arm64: dts: qcom: glymur: Add EVA clock controller node#1235
FROMLIST: arm64: dts: qcom: glymur: Add EVA clock controller node#1235taniyadas20 wants to merge 1 commit into
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Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. The EVACC provides clocks and resets to the EVA hardware block. Link: https://lore.kernel.org/r/20260526-evacc_glymur-v1-4-b61c7755c403@oss.qualcomm.com Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
…qualcomm-linux#1235) Hygon Family 18h CPUs are derived from AMD Family 17h (Zen1) silicon and share the same erratum qualcomm-linux#1235: hardware may read a stale IsRunning=1 bit during ICR write emulation and silently fail to generate an AVIC_IPI_FAILURE_TARGET_NOT_RUNNING VM-Exit on the sending vCPU. The absence of the VM-Exit causes KVM to miss the required wakeup of blocking target vCPUs, leading to hung vCPUs and unbounded delays in guest execution. Extend the existing AMD Family 17h erratum qualcomm-linux#1235 workaround to also cover Hygon Family 18h. With IPI virtualization disabled, KVM never sets IsRunning=1 in the Physical ID table, so every non-self IPI generates a VM-Exit and is correctly emulated. Fixes: 8de4a1c ("KVM: SVM: Disable (x2)AVIC IPI virtualization if CPU has erratum qualcomm-linux#1235") Cc: <stable@vger.kernel.org> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net> Message-ID: <20260522040014.3380201-1-zhang_wei@open-hieco.net>
Pull kvm fixes from Paolo Bonzini:
"arm64:
- Fix ITS EventID sanitisation when restoring an interrupt
translation table.
- Fix PPI memory leak when failing to initialise a vcpu.
- Correctly return an error when the validation of a hypervisor trace
descriptor fails, and limit this validation to protected mode only.
RISC-V:
- Fix invalid HVA warning in steal-time recording
- Return SBI_ERR_FAILURE to guest upon OOM in pmu_event_info() and
pmu_snapshot_set_shmem()
- Fix NULL pointer dereference in SBI v0.1 SEND_IPI handler
- Fix sign extension of value for MMIO loads
s390:
- Fix bugs in vSIE (nested virtualization) and UCONTROL, caused by
the page table rewrite.
x86:
- Apply erratum qualcomm-linux#1235 workaround (disable AVIC IPI virtualization) on
Hygon Family 18h, just like on AMD Family 17h.
- When KVM_CAP_X86_APIC_BUS_CYCLES_NS is queried on a specific VM,
return the VM's configured APIC bus frequency instead of the
default. This is less confusing (read: not wrong) and makes it
easier to fill in CPUID information that communicates the APIC bus
frequency to the guest.
Selftests:
- Do not include glibc-internal <bits/endian.h>; it worked by chance
and broke building KVM selftests with musl"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
KVM: SVM: Disable AVIC IPI virtualization on Hygon Family 18h (erratum qualcomm-linux#1235)
KVM: selftests: Verify that KVM returns the configured APIC cycle length
KVM: x86: Return the VM's configured APIC bus frequency when queried
KVM: selftests: elf: Include <endian.h> instead of <bits/endian.h>
KVM: s390: Properly reset zero bit in PGSTE
KVM: s390: vsie: Fix redundant rmap entries
KVM: s390: vsie: Fix unshadowing logic
KVM: s390: Fix leaking kvm_s390_mmu_cache in case of errors
KVM: s390: vsie: Fix memory leak when unshadowing
KVM: arm64: Fix nVHE/pKVM hyp tracing error on invalid desc
KVM: arm64: vgic: Free private_irqs when init fails after allocation
KVM: arm64: vgic-its: Reject restored DTE with out-of-range num_eventid_bits
RISC-V: KVM: Fix sign extension for MMIO loads
RISC-V: KVM: Fix NULL pointer dereference in SBI v0.1 SEND_IPI handler
riscv: kvm: return SBI_ERR_FAILURE for pmu_event_info() when OOM
riscv: kvm: return SBI_ERR_FAILURE for pmu_snapshot_set_shmem() when OOM
RISC-V: KVM: Fix invalid HVA warning in steal-time recording
🔨 Build Failure Analysis — PR #1235PR: #1235
Verdict1 of 1 errors is introduced by this PR. The build failure is caused by a missing dependency (dt-bindings header file). 📎 Detailed analysis: Full report |
PR #1235 — validate-patchPR: #1235
Final Summary
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PR #1235 — checker-log-analyzerPR: #1235
Detailed report: Full report
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Add the device node for the EVA clock controller (evacc) for Qualcomm Glymur SoC. The EVACC provides clocks and resets to the EVA hardware block.
Link: https://lore.kernel.org/r/20260526-evacc_glymur-v1-4-b61c7755c403@oss.qualcomm.com