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arm64: dts: qcom: add Shikra audio support #1239

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arm64: dts: qcom: add Shikra audio support #1239

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93218fa
arm64: dts: qcom: shikra-cqs-evk: add audio machine support
mpratyus May 26, 2026
0eb9985
arm64: dts: qcom: shikra: add audio, swr, and gpr support
mpratyus May 26, 2026
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238 changes: 235 additions & 3 deletions arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,56 @@
stdout-path = "serial0:115200n8";
};

sound {
compatible = "qcom,shikra-sndcard";
qcom,tdm-slots = <2>;
qcom,tdm-slot-width = <32>;
qcom,tdm-codec-slot-mask = <0x03>;

clocks = <&q6prmcc QAIF_CLK_ID_AUD_INTF2_IBIT LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "aud-intf2-ibit";

pinctrl-0 = <&i2s2_default>, <&dmic_eldo_en_defualt>;
pinctrl-names = "default";
model = "shikra-cqs-evk";

audio-routing = "VA DMIC0", "vdd-micb",
"VA DMIC1", "vdd-micb",
"VA DMIC2", "vdd-micb",
"VA DMIC3", "vdd-micb";

va-dmic-dai-link {
link-name = "VA DMIC Capture";

cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};

codec {
sound-dai = <&vamacro 0>;
};

platform {
sound-dai = <&q6apm>;
};
};

wsa-playback-dai-link {
link-name = "WSA Playback";

cpu {
sound-dai = <&q6apmbedai SECONDARY_TDM_RX_0>;
};

codec {
sound-dai = <&wsa885x_i2c>;
};

platform {
sound-dai = <&q6apm>;
};
};
};
lcd_bias: regulator-lcd-bias {
compatible = "regulator-fixed";
regulator-name = "lcd_bias";
Expand Down Expand Up @@ -76,6 +126,59 @@
};
};

&audiocorecc {
compatible = "qcom,shikra-cqs-audiocorecc";
};

&i2c3 {
status = "okay";

wsa885x_i2c: wsa885x-i2c-codec@c {
compatible = "qcom,wsa885x-i2c";
reg = <0x0c>;

pinctrl-names = "default";
pinctrl-0 = <&wsa885x_i2c_spkr_sd_n>;

interrupt-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vdd-1p8-supply = <&pm4125_l15>;
vdd-io-supply = <&pm4125_l15>;
qcom,battery_config = <2>;

wsa885x-init-table =
<0x8470 0x2 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_CLR(1) */
0x8470 0x0 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_CLR(0) */
0x8470 0x1 /* DIG_CTRL0_CDC_RXTX_FSCNT_CTL - FS_CNT_EN(1) */
0x0004 0x1 /* SMP_AMP_CTRL_STEREO_CMT_GRP_MASK - CMT_GRP_MASK(1) */
0x8602 0x60 /* CDC_RX0_RX_PATH_CFG1 - HPF_EN(0) */
0x8622 0x60 /* CDC_RX1_RX_PATH_CFG1 - HPF_EN(0) */
0x8458 0x79 /* PANDEIRO_DIG_CTRL0_VBAT_THRM_FLT_CTL - VBAT_COEF_SEL */
0x810B 0xD9 /* PANDEIRO_ANA_TOP_SPK_TOP_PWRSTG_CH1_TUNE3 */
0x8111 0xD9 /* PANDEIRO_ANA_TOP_SPK_TOP_PWRSTG_CH2_TUNE3 */
0x813C 0x08 /* SPK_TOP_COMMON_CTRL4 - override_ctl*/
0x8102 0x04 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_COMMON_CTRL2.LDO_PROG */
0x811C 0x29 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_LF_CH1_CTRL11.PHASE90(Add 90 degree phase shift between PWM clock of CH1 and CH2.) */
0x811D 0x40 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH1_TUNE1 - HIZ_DELAY_PROG*/
0x8129 0x40 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH2_TUNE1 - HIZ_DELAY_PROG*/
0x811A 0x80 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH1_CTRL9 - OCP_CLIP_T_CTRL_EXT */
0x8126 0x80 /* PANDEIRO_ANA_TOP_SPK_TOP_LF_CH2_CTRL9 - OCP_CLIP_T_CTRL_EXT */
0x8103 0x6 /* PANDEIRO_ANA_TOP_SPK_TOP_COMMON_TUNE1 - GAIN_TUNE */
0x80CA 0x85 /* PANDEIRO_ANA_TOP_IVSENSE_ADC_MODE_CTL2 - SPARE_BITS_0(Sets LDO to 1.6V) */
0x80CB 0xE /* PANDEIRO_ANA_TOP_IVSENSE_ADC_MODE_CTL3 - ADC_VREF_VCTL_I(Sets VREF_I to 1.35V) */
0x80CC 0xC /* PANDEIRO_ANA_TOP_IVSENSE_ADC_REF_CTL - ADC_VREF_VCTL_V(Sets VREF_V to 1.35V) */
0x80D0 0x80 /* PANDEIRO_ANA_TOP_IVSENSE_ADC_CDAC_CAL_CTL2 */
0x80BA 0xC0 /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.SPK_TOP_SPARE3(force the VDDSPK_LV_READY from analog to be high) */
0x841C 0x4E /* PANDEIROI2S.TOP.PANDEIRO_DIG_CTRL0_PANDEIRO_DIG_CTRL0.CDC_CLK_CTL.FSM_INTP_CG_DISABLE */
0x8435 0x47 /* PANDEIRO_DIG_CTRL0_PA1_FSM_CTL1 - SILENT_STATE_IVS_EN */
0x86CE 0x09 /* PANDEIROI2S.TOP.CDC_CLSH_CDC_CLSH.V1P8_BP_CTL2.BP_CNT */
0x8667 0x34 /* CDC_COMPANDER1_CTL7 - AGAIN_DELAY */
0x800D 0x08>; /* PANDEIROI2S.TOP.PANDEIRO_ANA_TOP.PON_CKSK_CTL_0 */

#sound-dai-cells = <0>;
};
};

&mdss_dsi0_out {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
Expand Down Expand Up @@ -114,9 +217,20 @@
};

&remoteproc_mpss {
firmware-name = "qcom/shikra/qdsp6sw.mbn";
firmware-name = "qcom/shikra/qdsp6sw.mbn";

status = "okay";
status = "okay";
};

&rxmacro {
clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_RX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&vamacro>;
clock-names = "mclk",
"npl",
"fsgen";

status = "okay";
};

&sdhc_1 {
Expand Down Expand Up @@ -151,7 +265,114 @@
status = "okay";
};

&spmi_bus {
pmic@0 {
pmic4125_codec: audio-codec@f000 {
compatible = "qcom,pm4125-codec";
reg = <0xf000>;
vdd-io-supply = <&pm4125_l15>;
vdd-cp-supply = <&pm4125_s1>;
vdd-pa-vpos-supply = <&pm4125_s1>;

vdd-mic-bias-supply = <&pm4125_l22>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;

qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;

qcom,rx-device = <&pm4125_rx>;
qcom,tx-device = <&pm4125_tx>;
#sound-dai-cells = <1>;

status = "okay";
};
};
};

&swr1 {
status = "okay";

pm4125_tx: codec@0,3 {
compatible = "sdw20217010c00";
reg = <0 3>;
qcom,tx-port-mapping = <2 2 3 4>;
};
};

&swr0 {
status = "okay";

pm4125_rx: codec@0,4 {
compatible = "sdw20217010c00";
reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5 >;
};
};

&tlmm {
dmic01_default: dmic01-default-state {
clk-pins {
pins = "gpio96";
function = "dmic";
drive-strength = <8>;
output-high;
};

data-pins {
pins = "gpio97";
function = "dmic";
drive-strength = <8>;
input-enable;
};
};

dmic23_default: dmic23-default-state {
clk-pins {
pins = "gpio98";
function = "dmic";
drive-strength = <8>;
output-high;
};

data-pins {
pins = "gpio99";
function = "dmic";
drive-strength = <8>;
input-enable;
};
};
dmic_eldo_en_defualt: dmic_eldo_en_default {
pins = "gpio71";
function = "gpio";
drive-strength = <8>; /* 8 mA */
bias-disable;
output-high;
};

i2s2_default: i2s2-default-active-state {
pins = "gpio100", "gpio101", "gpio102", "gpio103";
function = "i2s2";
drive-strength = <8>;
bias-disable;
};

i2s2_sleep: i2s2-sleep-state {
pins = "gpio100", "gpio101", "gpio102", "gpio103";
function = "i2s2";
drive-strength = <2>;
bias-disable;
};

wsa885x_i2c_spkr_sd_n: wsa885x-i2c-spkr-sd-n-active-state {
pins = "gpio2";
function = "gpio";
drive-strength = <8>;
input-disable;
output-enable;
};
lcd_bias_en: lcd-bias-en-state {
pins = "gpio151";
function = "gpio";
Expand Down Expand Up @@ -225,6 +446,18 @@
remote-endpoint = <&pm4125_ss_in>;
};

&vamacro {
pinctrl-0 = <&dmic01_default>, <&dmic23_default>, <&swr_tx_clk>, <&swr_tx_data0>;
pinctrl-names = "default";

clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "mclk", "npl";

qcom,dmic-sample-rate = <4800000>;
status = "okay";
};

&wifi {
vdd-0.8-cx-mx-supply = <&pm4125_l7>;
vdd-1.8-xo-supply = <&pm4125_l13>;
Expand All @@ -235,4 +468,3 @@

status = "okay";
};

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