arm64: dts: qcom: shikra: Update SDHC power-domain and interconnects#1252
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mchunara007 wants to merge 2 commits into
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arm64: dts: qcom: shikra: Update SDHC power-domain and interconnects#1252mchunara007 wants to merge 2 commits into
mchunara007 wants to merge 2 commits into
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Update the SDHC node to align with the RPM-based architecture of the
Shikra platform for eMMC device:
- Replace generic interconnect tags with RPM_ALWAYS_TAG and
RPM_ACTIVE_TAG.
- Switch the power domain from RPMh-based RPMHPD_CX to RPMPD-based
QCM2290_VDDCX.
- Update the 384 MHz OPP voltage requirement from NOM to SVS_PLUS to
optimally match the official clock plan.
Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
Add the QCM2290_VDDCX power domain and update interconnect tags to RPM-specific macros for SDHC2 to align with the Shikra platform architecture. Update the 202 MHz OPP to require the optimal voltage corner per the official hardware clock plan. Signed-off-by: Monish Chunara <monish.chunara@oss.qualcomm.com>
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This PR updates the SDHC1 and SDHC2 device tree nodes for the Shikra platform to properly align with its RPM-based power and interconnect architecture.
The changes focus on:
Interconnect Tags: Transitioning from generic QCOM_ICC tags to RPM-specific ALWAYS and ACTIVE tags to ensure correct bandwidth voting on this SoC topology.
Power Domains: Correcting the sdhc_1 definition (removing the RPMh typo) and adding the missing power domain to sdhc_2 using the RPMPD QCM2290_VDDCX ID.
OPP Alignment: Updating the voltage corner requirements for high-speed clock rates (384 MHz for sdhc_1 and 202 MHz for sdhc_2) to SVS_PLUS. This change aligns the software with the official hardware clock plan for improved power efficiency.