arm64: dts: qcom: purwa-iot-som: Add PM8010 camera PMIC regulators#549
arm64: dts: qcom: purwa-iot-som: Add PM8010 camera PMIC regulators#549tingguoc wants to merge 1 commit into
Conversation
shashim-quic
left a comment
There was a problem hiding this comment.
submit the change upstream and bring it as FROMLIST.
Add Link: to commit log.
Add the missing LDOs and supply parents so that camera sensor drivers can request the required power rails. L1M supplies the IMX688 AON core domain (DVDD). It is fed by S5J and supports an output range of 1056-1200 mV. L2M supplies the IMX766 core domain (DVDD). It is fed by S5J and supports an output range of 1152-1200 mV. L3M supplies the IMX766 analog domain and OV sensor I/O (AVDD2, DOVDD). It is fed by S4C and is fixed at 1808 mV. L5M supplies the IMX766 VCM. It is fed by BOB1 and is fixed at 2960 mV. L6M supplies the IMX688 AON analog domain (AVDD2). It is fed by S4C and is fixed at 1808 mV. L7M supplies the camera analog domain (AVDD). It is fed by BOB1 and is fixed at 2912 mV. Signed-off-by: Tingguo Cheng <tingguo.cheng@oss.qualcomm.com>
|
Merge Check Failed: No CR Numbers Found Error: No Change Request numbers were found. Please add Change Request numbers to your pull request description in the format CRs-Fixed: 12345 or link GitHub issues that are associated with Change Requests. |
PR #549 — validate-patchPR: #549
Final Summary
Recommendation:
|
PR #549 — checker-log-analyzerPR: #549
Detailed report: Full report
|
|
CRs-Fixed: 4552442 |
Add the missing LDOs and supply parents so that camera sensor drivers can request the required power rails.
L1M supplies the IMX688 AON core domain (DVDD). It is fed by S5J and supports an output range of 1056-1200 mV.
L2M supplies the IMX766 core domain (DVDD). It is fed by S5J and supports an output range of 1152-1200 mV.
L3M supplies the IMX766 analog domain and OV sensor I/O (AVDD2, DOVDD). It is fed by S4C and is fixed at 1808 mV.
L5M supplies the IMX766 VCM. It is fed by BOB1 and is fixed at 2960 mV.
L6M supplies the IMX688 AON analog domain (AVDD2). It is fed by S4C and is fixed at 1808 mV.