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Add pmsa defmt impls #164

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Merged
jonathanpallant merged 1 commit into from
May 3, 2026
Merged

Add pmsa defmt impls #164

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1 change: 1 addition & 0 deletions aarch32-cpu/CHANGELOG.md
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Expand Up @@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [Unreleased]

- Added `Iciallu` register which allows invalidating the instruction cache.
- Added `defmt` implementations for PMSA types.

## [aarch32-cpu v0.2.0]

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4 changes: 4 additions & 0 deletions aarch32-cpu/src/pmsav7.rs
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Expand Up @@ -189,6 +189,7 @@ impl Mpu {

/// Configuration for the PMSAv7 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Config<'a> {
/// Background Config Enable
///
Expand All @@ -202,6 +203,7 @@ pub struct Config<'a> {

/// Configuration for a region in the PMSAv7 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct Region {
/// The base address of this region.
///
Expand Down Expand Up @@ -232,6 +234,7 @@ unsafe impl Sync for Region {}

/// Describes the memory ordering and cacheability of a region
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum MemAttr {
/// Strongly-ordered memory
StronglyOrdered,
Expand Down Expand Up @@ -348,6 +351,7 @@ impl MemAttr {

/// A representation of Memory Attributes suitable for sticking into the RACR register
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
struct MemAttrBits {
tex: u3,
c: bool,
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8 changes: 8 additions & 0 deletions aarch32-cpu/src/pmsav8.rs
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Expand Up @@ -17,6 +17,7 @@ pub use register::prbar::{AccessPerms as El1AccessPerms, Shareability as El1Shar

/// Ways this API can fail
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Error {
/// Found too many regions
TooManyRegions,
Expand Down Expand Up @@ -363,6 +364,7 @@ impl El2Mpu {

/// Configuration for the PMSAv8-32 EL1 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct El1Config<'a> {
/// Background Config Enable
///
Expand All @@ -380,6 +382,7 @@ pub struct El1Config<'a> {

/// Configuration for the PMSAv8-32 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct El1Region {
/// The range of the region
///
Expand Down Expand Up @@ -408,6 +411,7 @@ unsafe impl Sync for El1Region {}

/// Configuration for the PMSAv8-32 EL2 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct El2Config<'a> {
/// Background Config Enable
///
Expand All @@ -425,6 +429,7 @@ pub struct El2Config<'a> {

/// Configuration for the PMSAv8-32 EL2 MPU
#[derive(Clone, Debug, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct El2Region {
/// The range of the region
///
Expand Down Expand Up @@ -453,6 +458,7 @@ unsafe impl Sync for El2Region {}

/// Describes the memory ordering and cacheability of a region
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum MemAttr {
/// Strongly-ordered memory
StronglyOrdered,
Expand Down Expand Up @@ -484,6 +490,7 @@ impl MemAttr {

/// Cacheability of a region
#[derive(Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum CachePolicy {
/// Normal memory, Outer Write-Through Transient
WriteThroughTransient(RwAllocPolicy),
Expand Down Expand Up @@ -512,6 +519,7 @@ impl CachePolicy {

/// Cache allocation policy
#[derive(Copy, Debug, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[repr(u8)]
pub enum RwAllocPolicy {
/// Write-allocate
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