I may be slow to respond.
MTech | Electronics Design Technology
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NIT Calicut
- India
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17:30
(UTC +05:30) - https://orcid.org/0009-0008-4983-6091
- in/saiprakashch
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zynq-dct-compression-ip
zynq-dct-compression-ip PublicAXI4-Lite custom IP core on Zynq-7000 (ZedBoard) implementing 2D 8×8 forward DCT, Zigzag scan, JPEG luminance quantization, and RLE encoding in hardware (Verilog). ARM Cortex-A9 PS drives the pipel…
Tcl 1
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sorting-techniques
sorting-techniques PublicImplementation of various sorting techniques in JAVA
Java 1
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