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feat: Add verilog support #428

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chuanseng-ng wants to merge 4 commits intotirth8205:mainfrom
chuanseng-ng:feature/add-sv-support
Open

feat: Add verilog support #428
chuanseng-ng wants to merge 4 commits intotirth8205:mainfrom
chuanseng-ng:feature/add-sv-support

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@chuanseng-ng chuanseng-ng commented May 5, 2026

Summary

  • Add verilog/system-verilog basic support in parser.py
    • Support module and interface declaration
    • Support package identifier

Scope

  • Verilog file-type (*.v, *.vh)
  • System-verilog file-type (*.sv, *.svh)
  • Packages (*.pkg)

Test

  • Add Verilog fixtures
  • Add Verilog tests in multilang.py

QA status

  • New tests passed via pytest
  • Ruff clean for modified points

Future support

  • Port & signal tracing

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