A study in MIPS microarchitecture trade-offs. This project implements three CPU designs: a single-cycle, a hardware-scheduled multicycle, and a software-scheduled pipelined core; then documents and contrasts their performance/complexity. Source is organized by variant (src_sc, src_hw, src_sw) with dedicated testbenches and write-ups.

custom CPU emulator and assembler

This is a simple CPU emulator with custom architecture

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

Its a RISC Architecture based 4-bit CPU made in Digital Logic Sim by Sebatsian Lague

RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

Computer Organization I exercises

RISCV 40 Instruction Cycle Accurate CPU Model

design of an 8-bit MPU

Replay-stable 64-bit 4-Way SMT-VLIW instruction-set emulator/runtime with streaming-vector transport, typed-slot scheduling, runtime-owned legality, replay evidence, and compiler/runtime structural agreement.

Custom instruction design on Mic-2 architecture for color-based blob detection