VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

All Digital Phase-Locked Loop (ADPLL)

PLL x8 clock multiplier IP integrated onto the Efabless Caravel SoC

Arduino controller programs for the ADF4351 PLL wideband frequency synthesizer with comprehensive register library following the ADF4351 datasheet. Includes manual control and automated sweep functionality.

This repository shows how to implement a simple PLL and a Frequency Meter using Arduino Uno.

Extract the 15MHz clock signal from 400 picosecond pulse train

Digital PLL design notes

Variants of a Phase-Locked Loop (PLL) on a FPGA in the Labview programming environment

Arduino library to communicate with Analog Devices ADF4110

Material from the course of Information Transmission at ENSEM - Université de Lorraine.

This is the open-access version of our CppSim-based fractional-N CP-PLL

IEEE TPEC 2026 publication showcase: a fast, robust grid-synchronization PLL using a Fixed-Frequency Enhanced ROGI (FF-EROGI) prefilter for three-phase grid-connected converters. Abstract, presentation, and citation (co-authored, presented at TPEC 2026).