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m2isar/backends/etiss/instruction_transform.py: add missing make_static for expr.right #87

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Merged
PhilippvK merged 1 commit into from
Apr 27, 2026
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m2isar/backends/etiss/instruction_transform.py: add missing make_static for expr.right #87

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2 changes: 2 additions & 0 deletions m2isar/backends/etiss/instruction_transform.py
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Original file line number Diff line number Diff line change
Expand Up @@ -699,6 +699,8 @@ def _(self, expr: behav.IndexedReference, context: TransformerContext):
# Use a simple base address on one site atleast for ranged_mem access.
# Index Codestring is forwarded into MemID class.
right = self.generate(expr.right, context)
if right.static and not context.ignore_static and not right.is_literal:
right.code = context.make_static(right.code, right.signed)
if(type(expr.index) == behav.NamedReference):
c.mem_ids.append(MemID(referred_mem, context.mem_var_count, index, size))
elif(type(expr.right) == behav.NamedReference):
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