Add Xilinx Zynq-7000 (ZC702) wolfBoot port

[dgarske]

Summary

Adds a wolfBoot port for the Xilinx Zynq-7000 SoC (Cortex-A9 dual-core, ARMv7-A 32-bit), verified end-to-end on the ZC702 Evaluation Kit (XC7Z020). This is a distinct port from the existing ZynqMP/zynq target -- different CPU architecture (A9 vs A53), different QSPI controller (XQspiPs vs XQspiPsu GQSPI), different SDHCI revision (Arasan v2.0 vs v3.0), and a simpler boot model (FSBL -> wolfBoot, no PMUFW/BL31).

Two configs, both verified on real ZC702 hardware:

Config	Storage	Payloads	Verified
config/examples/zynq7000.config	QSPI NOR (16 MB)	bare-metal and Linux (LINUX_PAYLOAD=1 MMU=1 ELF=1 -- one binary fits all three)	cold-boot pass for bare-metal; Linux 6.1.70 boots through full SMP init when paired with an appended-DTB zImage
config/examples/zc702_sdcard.config	SD card (MBR)	bare-metal	MBR + FAT32(BOOT.BIN) + 2 raw partitions (BOOT_A / BOOT_B); cold-boot pass

What's included

HAL (hal/zynq7000.{c,h,ld})

• UART driver (XUartPs UART1, 115200 8N1, MIO48/49 on the ZC702 J17 console).
• QSPI driver (XQspiPs -- the older Linear/Static QSPI on Z7, not the GQSPI on ZynqMP):
  • I/O mode for short command ops (RDID/RDSR/WREN/SE/PP) using the TXD1/TXD2/TXD3 auto-start FIFOs.
  • Linear/XIP mode for bulk reads via the memory-mapped 0xFC000000 window (32-bit AXI reads with byte unpack -- single-byte loads to the linear window are unreliable).
  • Wired to ext_flash_read/write/erase; hal_flash_* are no-ops (Z7 has no internal flash).
• SDHCI driver hooks (Arasan v2.0): translates the generic Cadence SD4HC layout used by src/sdhci.c to the Arasan standard SDHCI layout, plus SLCR clock + reset for the SDIO0 controller, plus ARMv7 D-cache maintenance via CP15 for SDMA.
• hal_get_timer_us via Cortex-A9 Global Timer at PERIPHCLK = CPU_3x2x = 333.33 MHz on the default ZC702 FSBL clock plan; feeds udelay() in the SDHCI driver.
• hal_prepare_boot: cleans+invalidates L1 D-cache by set/way, invalidates I-cache + branch predictor, disables MMU+caches via SCTLR before chain-load.
• Boot config banner in hal_init: prints storage type, post-init clock, payload ABI, partition addresses, and Global Timer frequency on every boot, so the UART log identifies which config the running image was built for.

Cortex-A9 startup (M8 -- generic ARMv7-A)

• src/boot_arm32_start.S rewritten as a generic ARMv7-A startup file (was SAMA5D3-specific). Now handles per-mode stacks (IRQ/FIQ/ABT/UND/SVC), VBAR setup, SCTLR.{A,V,C,I} clearing, TLB/I-cache/branch-predictor invalidate, async-abort enable, and .data/.bss setup. Used by both SAMA5D3 (Cortex-A5) and Zynq-7000 (Cortex-A9).
• src/boot_arm32.c do_boot rewritten as a single inline-asm block with proper operand/clobber annotations (avoids the cross-asm volatile-block register lifetime problem the previous version had). New WOLFBOOT_LINUX_PAYLOAD branch follows the ARM Linux boot ABI (r0=0, r1=~0, r2=DTB_phys, r3=0); default behavior (legacy DTS-in-r0) preserved when the flag is unset. Also fixes a stray mov r5, 0 -> mov r5, #0 so GAS accepts it in ARM mode.

Build system

• arch.mk Cortex-A9 block: -mcpu=cortex-a9 -mtune=cortex-a9 -marm plus FPU=-mfpu=vfp3-d16, pulls in the ARMv7-A SHA256 + SP-math objects, and gates MMU=1 -> -DMMU -DWOLFBOOT_FDT + src/fdt.o. DISK_SDCARD=1 pulls in src/sdhci.o, src/gpt.o, src/disk.o, src/update_disk.o. WOLFBOOT_UBOOT_LEGACY is gated on LINUX_PAYLOAD=1 (bare-metal builds shouldn't risk the ~1-in-2^32 false-positive collision against UBOOT_IMG_HDR_MAGIC).
• Makefile + test-app/Makefile: TARGET=zynq7000 plumbing.

Tools

• tools/scripts/zc702/zc702_qspi.bif -- bootgen template for BOOT.BIN (FSBL + wolfboot.elf), shared by all configs.
• tools/scripts/zc702/jtag_load.tcl -- xsdb script for JTAG-loaded development via Platform Cable II.
• tools/scripts/zc702/prepare_linux.sh -- signs zImage for the Linux config. Defaults to APPENDED=1 (concatenates DTB onto zImage and signs the pair as one wolfBoot image -- works around an ARMv7 zImage decompressor that loses r2 between entry and __atags_pointer on this kernel/load combo). APPENDED=0 for the raw-DTB-via-PART_DTS_BOOT path. Uses a whitelisted awk parser (no eval) to read the partition addresses out of .config.
• tools/scripts/zc702/prepare_sdcard.sh -- lays out a pure-MBR SD card (parted msdos + manual MBR type/active patch), formats p1 as FAT32, copies BOOT.BIN, dd's the signed image into raw partitions p2 and p3. Refuses /dev/sda, /dev/nvme*, /dev/mmcblk0, and non-removable block devices by default; explicit env-var overrides for the unusual cases.

Test app

• test-app/app_zynq7000.c + test-app/ARM-zynq7000.ld -- minimal banner + heartbeat dot loop over UART1 to validate the chain-load handoff. Uses int main(void) __attribute__((noreturn)) for portability.

Docs

• docs/Targets.md gets a complete "Xilinx Zynq-7000 (ZC702)" section: prerequisites (Vitis settings64.sh, Platform Cable II driver install, prebuilt FSBL clone), JTAG bring-up flow, explicit QSPI flashing recipe (program both BOOT.BIN and the signed payload), DDR map, sample cold-boot UART output, TEST_EXT_FLASH selftest expected output, SD-card boot table + Arasan v2.0 quirks, and a comparison table vs the ZynqMP port.

CI

.github/workflows/test-configs.yml adds two new build jobs (zynq7000_test, zc702_sdcard_test) using the existing test-build.yml reusable workflow with arch: arm and the wolfboot-ci-arm container image -- same setup the SAMA5D3 build uses, so no new toolchain is needed.

[Copilot]

Pull request overview

This PR adds an initial wolfBoot port for Xilinx Zynq-7000 on the ZC702 board, extending the codebase with a new ARMv7-A / Cortex-A9 target that boots via the Xilinx FSBL, verifies images from QSPI, and chain-loads a staged payload from DDR.

Changes:

• Adds a new zynq7000 target across the HAL, startup code, linker scripts, and build system for FSBL-loaded Cortex-A9 boot.
• Introduces a Zynq-7000 QSPI/UART HAL, RAM-boot configuration, and a minimal test application for bring-up validation.
• Documents the target, JTAG workflow, QSPI layout, and adds helper scripts for XSDB/bootgen usage.

Reviewed changes

Copilot reviewed 14 out of 14 changed files in this pull request and generated 1 comment.

Show a summary per file

File	Description
tools/scripts/zc702/zc702_qspi.bif	Adds a bootgen BIF template for packaging FSBL + wolfBoot into BOOT.BIN.
tools/scripts/zc702/jtag_load.tcl	Adds an XSDB script for JTAG bring-up by running FSBL and loading wolfboot.elf into DDR.
test-app/app_zynq7000.c	Adds a minimal bare-metal ZC702 test app that prints a boot banner and heartbeat on UART1.
test-app/Makefile	Wires the new target into test-app builds with the ARM32 startup object and target linker script.
test-app/ARM-zynq7000.ld	Adds the linker script for the staged Zynq-7000 test application in DDR.
src/boot_zynq7000_start.S	Adds Zynq-7000-specific ARMv7-A startup, vector setup, stack initialization, and early CPU state handling.
src/boot_arm32.c	Adjusts ARM32 inline assembly immediate syntax used during chain-load handoff.
hal/zynq7000.ld	Adds the wolfBoot linker script for execution from DDR at the FSBL handoff address.
hal/zynq7000.h	Defines Zynq-7000 register maps and bitfields for UART, QSPI, and related peripherals.
hal/zynq7000.c	Implements the new Zynq-7000 HAL, including UART, QSPI external flash access, and boot-preparation logic.
docs/Targets.md	Documents the new ZC702 target, configuration, memory map, JTAG flow, and expected output.
config/examples/zynq7000.config	Adds an example configuration for ECC256/SHA256 RAM-boot from external QSPI flash.
arch.mk	Adds target selection and Cortex-A9-specific compiler/object settings for zynq7000.
Makefile	Includes the new target in the default main build outputs.

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.

[Copilot]

Pull request overview

Copilot reviewed 19 out of 19 changed files in this pull request and generated 9 comments.

[Copilot]

Pull request overview

Copilot reviewed 18 out of 18 changed files in this pull request and generated 8 comments.

[Copilot]

Pull request overview

Copilot reviewed 18 out of 18 changed files in this pull request and generated 8 comments.