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Pull requests: llvm/circt
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[Datapath] Implement Add with Carry-In to Improve Subtraction Circuit Implementation
#9949
opened Mar 16, 2026 by
sarthakmangla1
•
Draft
1 task
[ImportVerilog][Sim] Added remaining Moore instructions for dynamic arrays, as well as the corresponding Sim dialect instructions
#9944
opened Mar 15, 2026 by
yuriyKulinchenko
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[Synth] Add basic SAT construction for functional reduction
#9939
opened Mar 14, 2026 by
uenoku
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[FIRRTL] Add lowering for firrtl.domain.subfield operations
#9933
opened Mar 13, 2026 by
seldridge
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[ImportVerilog] Fix moore.conversion legalization failure on interface ports
#9927
opened Mar 13, 2026 by
Mohamed-Khairy-SWE
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[ImportVerilog] Convert arity-based system task to named-based matching
ImportVerilog
#9923
opened Mar 12, 2026 by
fabianschuiki
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[FIRRTL] Add configuration file support for FIRRTL instance choices
#9870
opened Mar 7, 2026 by
uenoku
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[ImportVerilog] Introduce the semantic analysis of slang
#9862
opened Mar 6, 2026 by
sunhailong2001
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[circt-bmc] Add multi-clock BMC support via independent toggling
#9803
opened Mar 1, 2026 by
robert-at-pretension-io
•
Draft
[ImportVerilog] Implement procedural continuous assignment
#9795
opened Mar 1, 2026 by
Arya-Golkari
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[HW] HWVectorization Part 3: Structural Patterns
#9749
opened Feb 24, 2026 by
mafeguimaraes
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[FIRRTL] Add CheckInstanceChoice pass to reject nested instance choices
#9743
opened Feb 24, 2026 by
uenoku
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