firtool-1.142.0

What's Changed

• [Arc] Fix extraneous semicolons in TraceEncoder; NFC by @fabianschuiki in #9746
• [circt-bmc] Add LTLToCore to pipeline by @TaoBi22 in #9735
• [HW][circt-reduce] Add HW name sanitization by @seldridge in #9730
• Move ESI runtime tests into pytest suite by @teqdruid in #9655
• [CI] Cancel in-progress PR builds on new push by @Copilot in #9751
• [ImportVerilog][MooreToCore][Sim] Support queue element/range extractions in ImportVerilog and Sim by @Lauriethefish in #9727
• [Synth] Add resource usage analysis by @uenoku in #9717
• [HW] Make sure the index type for arrays is at least i1 by @pscabot in #9733
• [ImportVerilog] Make sampled value functions' results usable by Moore ops by @Arya-Golkari in #9718
• [ImportVerilog] Support $ literal within queue indexing expressions by @Lauriethefish in #9719
• [circt-reduce] Use per-port matching for FIRRTL port pruners by @seldridge in #9755
• [Arc] Add time operations for LLHD simulation support by @fabianschuiki in #9747
• [FIRRTL] Allow full reset module instances outside of reset domain by @fabianschuiki in #9754
• [HWToLLVM] Take the correct data layout alignment for alloca by @pscabot in #9734
• [FIRRTL][LowerToHW] Add InstanceChoiceOp lowering, Part 1 by @uenoku in #9742
• [FIRRTL] Fix domain info updates in cloneWithInsertedPorts by @seldridge in #9758
• [Datapath] Bug Fix for Sign-Extension Logic when Lowering Partial Products to Booth Arrays (#9726) by @cowardsa in #9744
• [ESI] Update test to exercise new functionality by @teqdruid in #9763
• [PyRTG] Add String format function by @maerhart in #9762
• [ESI][Runtime] Support editable installs by @teqdruid in #9764
• [ESI][Runtime] Improve support for extending pytest.cosim_test by @teqdruid in #9765
• [FIRRTL] Add instance macro attribute to InstanceChoice for Lowering by @uenoku in #9760
• [FIRRTL] Lazily construct CircuitNamespace, NFC by @uenoku in #9767
• [FIRRTL] Support FInstanceLike operations in ModuleInliner by @uenoku in #9688
• [ESI][Runtime] Don't crash on unsupported type by @teqdruid in #9768
• [PyCDE] Remove python 3.8, 3.9 and add 3.14 builds by @teqdruid in #9769
• [PyCDE] Disable cocotb tests by default by @teqdruid in #9770
• [Arc] Lower llhd.current_time to Arc in LowerState by @fabianschuiki in #9756
• [FIRRTL] Add domain create op by @seldridge in #9774
• [FIRRTL] Improve error messages for domain symbol verification by @seldridge in #9776
• [Moore][ImportVerilog] Add support for fork-join blocks by @tdps2 in #9682
• [FIRRTL] Add conservative IMDCE handling for InstanceChoiceOp by @uenoku in #9710
• [Arc] Lower time operations to LLVM IR by @fabianschuiki in #9757
• [FIRRTL] Support merging layers in LinkCircuits by @unlsycn in #9677
• [ImportVerilog] Add support for $swrite by @fabianschuiki in #9782
• [Moore] Add %m/%M hierarchical path format specifier by @fabianschuiki in #9783
• [Comb] [NFC] Reorder arguments for the consistency in CombOps create* helpers by @uenoku in #9799
• [RTG] Same seed for all tests & random scopes by @maerhart in #9793
• [RTG][Elaboration] Fix getUniformInRange by @maerhart in #9806
• [PyCDE] Fix Struct metaclass for Python 3.14 (PEP 649/749 annotations) and CI disk space by @Copilot in #9773
• [circt-verilog] Bump slang version requirement to 10.0 by @unlsycn in #9808
• [ImportVerilog][Sim][MooreToCore] Add support for resizing queues by @Lauriethefish in #9780
• [Arc] Use simulation time for VCD timestamps by @fabianschuiki in #9785
• [Moore][MooreToCore][Sim] Support for basic uses of moore.dyn_queue_ref_element by @Lauriethefish in #9778
• [ImportVerilog][Moore] Add support for queue concatenations by @Lauriethefish in #9777
• [ESI Runtime] Add statically typed port wrappers by @teqdruid in #9771
• [ESI] Add ValidOnly channel signaling protocol by @teqdruid in #9787
• [ESI][Copilot] Add ESI runtime development skills file by @teqdruid in #9812
• [Comb] Officialize support for zero-width integers by @Moxinilian in #6959
• [SV] Add an utility function to construct nested ifdefs by @uenoku in #9798
• [FIRRTL] Allow keywords as identifiers in expressions by @seldridge in #9788
• [ImportLiberty] Remove unused functions, NFC by @uenoku in #9813
• [FIRRTL] Add case_macro attribute to OptionCaseOp and refactor PopulateInstanceChoiceSymbols by @uenoku in #9797
• [FIRRTL][LowerToHW] Require instance_macro before lowering by @uenoku in #9814
• [FIRRTL] Allow Unknown as an identifier by @seldridge in #9789
• [RTG][circt-tblgen] Add RegisterAllocationOpInterface methods and decorators by @maerhart in #9801
• [VerifToSMT] Add meaningful name prefixes to BMC symbolic constants by @5iri in #9794
• [ImportVerilog] Add support for associative array extractions by @Elijah-Cheesman in #9796
• [HWToBTOR2][NFC] Fix typo in multi-clock error by @TaoBi22 in #9819
• [Synth][CutRewriter] Add LogicNetwork flat IR by @uenoku in #9804
• [Synth][CutRewriter] Migrate CutRewriter to use Flat IR by @uenoku in #9805
• [ESI][Cosim][Pytest] Increase debug-ability of cosim pytest runs by @teqdruid in #9825
• [Tools] Set bug report messages to CIRCT by @uenoku in #9826
• [Synth][CutRewriter] Add a LEC test for mig/xor, NFC by @uenoku in #9828
• [FSM] Convert FSM to SMT by @luisacicolini in #9379
• [FIRRTL][Inliner] Fix NLA updates during flattening by @seldridge in #9810
• [ImportVerilog] Add delete and clear ops for assoc arrays by @Elijah-Cheesman in #9823
• [FIRRTL][Inliner] Remove flattenPoint, use inlinedSymbols by @seldridge in #9816
• [RTG][circt-tblgen] Auto-generate instruction assembly and binary emission methods by @maerhart in #9802
• [ImportVerilog] Support DPI-C extern declarations and open arrays by @pscabot in #9809
• [FIRRTL] InstanceChoice support for LowerToHW, Part 2(ABI lowering) by @uenoku in #9761
• [FIRRTL][LowerDomains] Add support for DomainCreateOp by @seldridge in #9781
• [Synth][CutRewriter] Fix potential non-determinism by @uenoku in #9830
• [LowerToHW] Use "-" for instance choice header file delimiter by @uenoku in #9832
• [Synth][SOPBalancing] Fix non-determinism from duplicated value numbering by @uenoku in #9836
• [FIRRTL] Use hw.hierpath in CreateSiFiveMetadata by @seldridge in #9829
• [HWToBTOR2] Strengthen multi-clocking detection by @TaoBi22 in #9820
• Update to avoid arith i0 by @jpienaar in #9835
• [ImportVerilog] Waive another valgrind test, NFC by @seldridge in #9841
• [Handshake] Fix deprecated builder.create warnings by @seldridge in #9843
• [SV] Remove extract-test-code by @rwy7 in #8846

New Contributors

• @tdps2 made their first contribution in #9682
• @Elijah-Cheesman made their first contribution in #9796

Full Changelog: firtool-1.141.0...firtool-1.142.0

firtool-1.141.1

Full Changelog: firtool-1.141.0...firtool-1.141.1

firtool-1.141.0

What's Changed

• [RTG] InlineSequences: best-effort mode and traverse nested regions by @maerhart in #9568
• [MooreToCore] Add ToBuiltinInt bitcast conversion by @TaoBi22 in #9591
• [Docs] Continuing migration of documentation to a single Tools page by @cowardsa in #9589
• [circt-reduce] Fix module-name-sanitizer crash with objects by @seldridge in #9584
• [circt-reduce] Fix instance-stubber: ref/property by @seldridge in #9580
• [ImportVerilog] Swap Statements conditions to ToBuiltinInt by @TaoBi22 in #9594
• [RTG][Elaboration] Support symbolic values more generically by @maerhart in #9577
• [circt-reduce] Fix extmodule-instance-remover crash with strings by @seldridge in #9582
• [circt-reduce] Fix firrtl-remove-unused-ports crash with probes by @seldridge in #9583
• [FIRRTL] Add asReset cast op by @fabianschuiki in #9596
• [FIRRTL] Fix canonicalizer infinite loop with const types by @seldridge in #9595
• [circt-reduce] Add FIRRTL LayerDisable reduction by @seldridge in #9599
• [SV] Add elaboration and run-time error/warning/info operations to SV dialect by @uenoku in #9601
• [FIRRTL][CAPI] Update RefType creation to support layers by @unlsycn in #9600
• [Moore] Remove ToBuiltinBoolOp by @TaoBi22 in #9605
• [circt-reduce] Add list-create-element-remover reduction by @seldridge in #9603
• [MooreToCore] Add UnionType conversion support (Fixes #9570) by @m2kar in #9571
• [MooreToCore] Add NoOpConversion by @TaoBi22 in #9607
• [Moore] Add from_builtin_int op by @TaoBi22 in #9606
• [FIRRTL] Make UnknownValueOp CSE-able by @seldridge in #9608
• [MooreToCore] Emit error for unsupported module port types by @m2kar in #9575
• [datapath] Signed Partial Product Generation by @cowardsa in #9592
• [FIRRTL] Add asReset cast support to InferWidths and InferResets by @fabianschuiki in #9610
• Implement support for DisableIff in assertions by @Lauriethefish in #9612
• Update LTL rationale: remove mention of ltl.disable by @Lauriethefish in #9613
• [Python] Add HLMemType and FirMemType bindings to Seq dialect by @yassinz in #9585
• [FIRRTL] Generate annotation code from tablegen by @youngar in #9604
• Bump LLVM to 972cd847efb20661ea7ee8982dd19730aa040c75. by @mikeurbach in #9618
• [ImportVerilog] Make $past result usable by Moore ops by @TaoBi22 in #9621
• [ESI][PyCDE] Support for serial lists by @teqdruid in #9627
• [OM][Evaluator][domaintool] Drop Kind::Unknown by @seldridge in #9617
• [RTG] Add StringType and basic string ops by @maerhart in #9622
• [RTG] Use string values for comments and error messages by @maerhart in #9623
• [ESI] Move runtime test into pycde integration tests by @teqdruid in #9628
• [RTG] More powerful string formatting for labels by @maerhart in #9631
• [Moore] Add builtin for $urandom_range by @Arya-Golkari in #9629
• [datapath] Signed compressor arguments by @cowardsa in #9620
• [Comb] Add a transform to ensure division does not trap/SIGFPE by @jmolloy in #9619
• [ImportVerilog] Allow $past with non-boolean bitvecs by @TaoBi22 in #9626
• [FIRRTL] Add missing #include by @jmolloy in #9636
• [HW] Fix ArrayCreateOp verifier to support typealiases and add optional result type syntax by @Copilot in #9639
• [domaintool] Use type-based domain assignment by @seldridge in #9630
• [Python] Add "result_type" on ArrayCreateOp by @teqdruid in #9640
• [ImportVerilog] Add queue insert/delete ops by @Lauriethefish in #9632
• [ESI][Runtime] Add support for TypeAlias and python for AnyType by @teqdruid in #9641
• [OM] Add reduction patterns for circt-reduce by @seldridge in #9624
• [LTL] Add optional clock operand to PastOp by @TaoBi22 in #9644
• [RTG] Improve source location tracking in some passes by @maerhart in #9645
• [ESI][Runtime] Add C++ type code generation by @teqdruid in #9642
• [PyRTG] Print location information in MLIR output by @maerhart in #9646
• [comb] New Canonicalization ~sext(x) = sext(~x) by @cowardsa in #9637
• Add support for $changed by @Arya-Golkari in #9634
• [ImportVerilog] Fix incorrect changed PastOp construction by @TaoBi22 in #9652
• [Docs] fix typo in Charter.md by @nilscrm in #9650
• [Docs] Remove nonexistent LTL op from LTL rationale by @TaoBi22 in #9653
• [FIRRTL] Refactor LowerTypes to use linear-time port removal, NFC by @uenoku in #9647
• [ESI][Runtime] Fix Windows cibuildwheel builds by @teqdruid in #9616
• [Docs] Fixed small error in SVA representation of $changed in LTL documentation by @Arya-Golkari in #9659
• [FIRRTL][SpecializeOption] Preserve unselected options by @uenoku in #9664
• [FIRRTL] Add pre-allocation for SmallVector, NFC by @uenoku in #9666
• [FIRRTL][LowerXMR] Add inner symbols directly when possible by @seldridge in #9657
• [MooreToCore] Support moore.from_builtin_int as a NoOpConversion by @Arya-Golkari in #9658
• [MooreToCore][Sim] Implementation of queues in Sim by @Lauriethefish in #9651
• [RTG] Add array_append operation by @maerhart in #9662
• [FIRRTL] Add InstanceGraphInstanceOpInterface to InstanceChoiceOp by @uenoku in #9523
• [FIRRTL][LowerLayers] Add inner symbols directly when possible by @seldridge in #9654
• [FIRRTL][LowerSignature] Support InstanceChoice in LowerSignature by @uenoku in #9665
• [circt-verilog] bump Slang to 10.0 by @TaoBi22 in #9667
• [FIRRTL][circt-reduce] Improve port reductions by @seldridge in #9660
• [FIRRTL][OM] Use signed integer attributes by @rwy7 in #9548
• [Sim][MooreToCore] Implement queue insert/delete/(clear) ops by @Lauriethefish in #9668
• [CombFolds] Improve m_Complement matcher to allow pattern nest by @uenoku in #9663
• [HandshakeToHW] Fix crashes when multiple syncs with different numbers of none inputs are used by @zhengyao-lin in #9587
• [MooreToCore] Add support for $info by @Arya-Golkari in #9672
• [MooreToCore] Add pattern for conversion of NegRealOp by @fzi-hielscher in #9678
• [HWAggregateToComb] Support hw.sturct_extruct and hw.struct_create by @uenoku in #9675
• [FIRRTL] Change FInstanceLike to consider multiple referred modules by @uenoku in #9676
• [ImportVerilog] Modify sampled value functions to use Comb operators by @Arya-Golkari in #9656
• [Arc] Add dialect documentation by @fabianschuiki in #9685
• Enable vcpkg binary caching for ESI Runtime Windows wheel builds by @Copilot in #9691
• [FIRRTL][Reduce] Fix module-port-pruner crash with probe ports by @seldridge in #9694
• [ImportVerilog] Pass library files to slang by @rhanqtl in #9680
• [FIRRTL][IMCP] Add conservative support for InstanceChoiceOp by @uenoku in #9692
• [FIRRTL][LayerSink] Support InstanceChoice by @uenoku in #9696
• [FIRRTL] Dedup: fix non-deduplicatable public module handling by @youngar in #9702
• [LTL][ImportVerilog] Add support for $sampled by @Arya-Golkari in #9673
• [LLHD] teach Deseq about projected fields via ValueField keys by @5iri in #9588
• [MooreToCore] Support all NetOp kinds by @rhanqtl in #9635
• [RTG][Elaboration] Materialize values via attributes when possible by @maerhart in #9703
• [PyRTG] Add instruction decorator by @maer...

firtool-1.140.0

What's Changed

• [circt-bmc] don't error when no assertions are given by @TaoBi22 in #9433
• [Synth] Extract delay-aware tree building into reusable utility, NFC by @uenoku in #9430
• [LLHD] Add support for IntegerType to SROA by @jmolloy in #9386
• [circt-synth] Add pre-synthesis optimization passes by @uenoku in #9428
• [ArcRuntime] Add runtime library implementation for arcilator by @fzi-hielscher in #9356
• [FIRRTL] Domain inference by @rwy7 in #9106
• [Arc][ArcToLLVM] Add RuntimeModelOp by @fzi-hielscher in #9435
• [Arc][ArcToLLVM] Add InsertRuntime pass by @fzi-hielscher in #9357
• [arcilator][ArcRuntime] Integrate ArcRuntime by @fzi-hielscher in #9358
• [Sim] Add dynamic string type and basic ops by @KavyaChopra04 in #9438
• [LLHD] Fix multiply-driven signals being hoisted incorrectly by @fabianschuiki in #9421
• [circt-bmc] Move no assertions check into VerifToSMT by @TaoBi22 in #9441
• [ESI][RpcClient] Prevent deadlock on disconnect by @mortbopet in #9440
• [ESI][Runtime] Add cycle count and frequency to SysInfo by @teqdruid in #9423
• [NFC][VerifToSMT] Clean up initial value checks by @TaoBi22 in #9445
• Bump LLVM to f091be6d53e447391ca23142cf9d49b2654116d7 by @jpienaar in #9443
• [FIRRTL][FlattenMemory] Change FlattenMemory to also convert base types to UInt by @fzi-hielscher in #9448
• [ImportVerilog] Don't wrap concurrent assertions in ProcedureOps by @TaoBi22 in #9451
• Cleanup to no longer use deprecated make_scope_exit by @nigham in #9432
• Reduce import test to avoid flagged cases by @jpienaar in #9450
• [HW] Verify inner symbols InnerSymbolTable ports. by @dtzSiFive in #9447
• [circt-test] Add dynamic progress display; various usability tweaks by @fabianschuiki in #9452
• [ImportLiberty] Add Liberty file parser for circt-translate by @uenoku in #9439
• [Sim] Rework constant folding of sim.fmt.* operations by @fzi-hielscher in #9455
• [PyCDE] Fix seq.compreg name handling after LLVM submodule bump by @teqdruid in #9457
• [ESI] Fix memory leak in wrap operation folders by @teqdruid in #9458
• [ESI] Allow snoop operations on channels without unwrap by @teqdruid in #9459
• [Doc] Fix missing line continuation character in CMake build example by @m2kar in #9461
• [FIRRTL] Support special format substitutions in Chisel verification intrinsics by @uenoku in #9460
• [Synth] Refactor CutRewritePattern to return area/delay from match() by @uenoku in #9434
• Ignore additional property ports on firrtl.simulation target modules by @trmckay in #9462
• [ESI][Runtime] Always link nanobind module to static stdc++ by @teqdruid in #9463
• [FIRRTL][InferResets] Fix reset domain inference for multiple top-level modules by @uenoku in #9464
• [Comb] Replace BoolArrayAttr with DenseBoolArrayAttr in TruthTableOp by @uenoku in #9465
• [FIRRTL] Extend LinkCircuits to handle extmodule collisions by @unlsycn in #9404
• [Arc] Add nascent support for sim.proc.print and sim.fmt.* by @jmolloy in #9442
• [verif] Add combine-assert-like pass by @dobios in #9437
• [LTLToCore] Add core lowering for boolean implication by @TaoBi22 in #9456
• [LTLToCore] Add not, and, or lowerings by @TaoBi22 in #9478
• [cmake] consistently use includedir dest var for headers by @dtzSiFive in #9475
• [MooreToCore][Sim] added int-to-string support by @KavyaChopra04 in #9473
• [ImportLiberty] Treat space as logical AND in expression parser by @uenoku in #9470
• [FIRRTL] Drop domain associations w/ zero-width by @seldridge in #9477
• [FIRRTL] Same defname ExtModules in LowerClasses by @seldridge in #9472
• [Arc][Python] Add Arc dialect type property getters to Python bindings by @yassinz in #9484
• [circt-bmc] Add CombineAssertLike to pipeline by @TaoBi22 in #9479
• [ArcRuntime] Minor fixes and tweaks to ArcRuntime headers by @fzi-hielscher in #9486
• Add circt-tblgen, generate FIRRTL intrinsics docs by @fabianschuiki in #9454
• [VerifToSMT] Consider assertions inside funcs by @TaoBi22 in #9487
• [FIRRTL] Add folders for IntegerShrOp by @stomfaig in #9401
• [MooreToCore][Moore][ImportVerilog] Add basic ops for dynamic string type by @KavyaChopra04 in #9480
• [SV] Add InnerRefUserOpInterface to sv.verbatim by @uenoku in #9492
• [Support] [Synth] Rename NPNClass to TruthTable and add cofactor utilities by @uenoku in #9493
• Update .clang-format to disable TableGen by @uenoku in #9499
• [ImportVerilog] Add support for parameter-typed class member access by @Scheremo in #9500
• [circt-bmc] add hw-flatten-modules to pipeline by @TaoBi22 in #9495
• [hw-flatten-modules] Add option to inline public modules by @TaoBi22 in #9501
• [circt-bmc] Allow public module inlining by @TaoBi22 in #9502
• [Arc] Add onInitialized runtime hook by @fzi-hielscher in #9497
• [Arc] Add TraceTap attribute and annotate StateWriteOps of named states by @fzi-hielscher in #9498
• Add attribute to track external requirements for external and verbatim modules by @trmckay in #9496
• [Support] Add ISOP extraction utilities to TruthTable by @uenoku in #9506
• [ImportVerilog] Fix class method prototype resolution by @Scheremo in #9508
• [ImportVerilog] Implement support for null literals by @Scheremo in #9509
• [circt-opt] Add pass --convert-core-to-fsm by @AtticusKuhn in #8852
• [CoreToFSM] Cleanup non-deterministic iteration by @TaoBi22 in #9513
• [NFC][CoreToFSM] Drop unused variables by @TaoBi22 in #9514
• [CoreToFSM] Swap to Op::create by @TaoBi22 in #9515
• [CoreToFSM] Don't discard pattern driver result by @TaoBi22 in #9518
• [ImportVerilog] Add support for static class members by @Scheremo in #9517
• [py] Enable using default context in StructType.get by @jpienaar in #9512
• [Arc] Stabilize order in ModelInfoAnalysis, NFC by @fzi-hielscher in #9522
• [Synth] Add SOP balancing pass for delay optimization by @uenoku in #9511
• [LTL] Make PastOp return an i1 by @TaoBi22 in #9525
• [ImportVerilog] Add support for queue size() builtin by @Scheremo in #9524
• [ImportVerilog] add handle comparison ops and lower ==/!=/===/!== by @Scheremo in #9520
• [ImportVerilog] Allow static member hoisting from outside class by @Scheremo in #9521
• [ImportVerilog] Use comb.xor instead of ltl.not in $rose lowering by @TaoBi22 in #9526
• [FIRRTL][OM] Add, evaluate UnknownValueOp by @seldridge in #9474
• [FIRRTL] AnnotateInputOnlyModules: Skip modules with enabled layers by @uenoku in #9485
• [ImportVerilog] Fix class conversion crashes by @Scheremo in #9527
• [Arc] Add trace encoding infrastructure to ArcRuntime by @fzi-hielscher in #9503
• [Arc] Implement VCD trace encoder for ArcRuntime by @fzi-hielscher in #9504
• [LTL] Allow PastOp to take integer inputs by @TaoBi22 in #9532
• [ImportVerilog] Add support for unary $past builtin by @TaoBi22 in #9531
• [Synth][LongestPathAnalysis] Fix an incorrect instanch path by @uenoku in #9536
• [Arc] Add trace instrumentation to arcilator pipeline by @fzi-hielscher in #9505
• [Moore] Add ToBuiltinIntOp by @TaoBi22 in #9533
• ...

firtool-1.139.0

What's Changed

• [FIRRTL][GrandCentral] Add -no-views option. by @dtzSiFive in #9304
• [FIRRTL] Remove -allow-adding-ports-on-public-modules. by @dtzSiFive in #9301
• [verif] Add canonicalizers of clocked assertlikes by @seldridge in #9307
• [ESI] Include more WindowType info in manifest by @teqdruid in #9308
• Bump LLVM by @uenoku in #9306
• [FIRRTL] Use type inference for domain anon op by @rwy7 in #9312
• Document Copilot build setup (incl. PyCDE/ESI) and align integration image defaults by @Copilot in #9314
• [HW] Extend ElementType parsing to support union types by @yassinz in #9318
• [ESI][Runtime] Add non-list Window type read translations by @teqdruid in #9319
• [ESI][Runtime] Add non-list Window type write translations by @teqdruid in #9324
• [FIRRTL] Allow domain ports after associations by @seldridge in #9323
• [Verif] Add hw.constant Verif canonicalizers by @seldridge in #9325
• [ExportVerilog] Move declarations to the top of blocks when disallowDeclAssignments is set. by @uenoku in #9309
• [FIRRTL] Remove nonlocal field from annotations when NLA becomes local by @uenoku in #9329
• [ESI][Runtime] Translate message performance enhancements by @teqdruid in #9330
• [ESI][Runtime] Port Python bindings from pybind11 to nanobind by @Copilot in #9322
• [Python][LLVM] Add LLVM dialect and modify export llvm ir test by @yassinz in #9316
• [FIRRTL] Don't create empty modules in LowerLayers by @seldridge in #9333
• [FIRRTL] Fix Dedup issue caused by name shadowing by @fabianschuiki in #9336
• [ESI][Runtime] Parallel encoded list translation support by @teqdruid in #9334
• [FIRRTL][Dedup] Improve error messages for nested bundle type mismatches by @uenoku in #9338
• [FIRRTL][firtool] Add --inline-input-only-modules option to firtool by @uenoku in #9332
• [ESI] Improve RpcServer/CosimBackend usability through distributed package by @mortbopet in #9339
• [ImportVerilog][MooreToCore] Added support for int_to_real by @KavyaChopra04 in #9317
• [Sim][MooreToCore] Added octal formatting specifier for printing integers by @KavyaChopra04 in #9343
• Reapply "[circt-lsp-server] Make time source injectable" by @uenoku in #9342
• [Python][Sim] Bind sim dialect to python by @teqdruid in #9345
• [MooreToCore] Added real_to_int support by @KavyaChopra04 in #9346
• [LLHD] Fix HoistSignals with non-uniform drive delays by @fabianschuiki in #9349
• [ImportVerilog] Fix class property segfault and emit error by @fabianschuiki in #9347
• [Datapath] Convert comparison operators to arithmetic - avoiding multiple carry propagate adders by @cowardsa in #9344
• [PyCDE] Emit $info messages by @teqdruid in #9351
• [ESI] Factor out gRPC/proto usage in Cosim backend by @mortbopet in #9350
• [MooreToCore] Support float comparison operations by @maerhart in #9355
• [Arc] Use explicit CompReg reset instead of mux by @TaoBi22 in #9359
• [RTG] Add virtual register reduction pattern by @maerhart in #9283
• [ImportVerilog][Moore] Use more specific casting operations for string, real, and time casts by @maerhart in #9352
• [arcilator] add option to treat async firreg resets as sync by @TaoBi22 in #9360
• [MooreToCore] Support binary real operations by @maerhart in #9362
• [ESI][RpcClient] Implement synchronization for RPC completion by @mortbopet in #9363
• [ImportVerilog] Convert realtime values to f64 before operations by @maerhart in #9364
• [ImportVerilog] Properly cast subroutine call result value by @maerhart in #9365
• [ImportVerilog] Cast func call arguments to types matching func decl by @maerhart in #9366
• [ImportVerilog] Add support for program definitions by @fabianschuiki in #9377
• [MooreToCore] Lower $time to new LLHD current time op by @fabianschuiki in #9378
• [Seq] Update HWMemSimImpl's replSeqMem to support higher latency. by @mikeurbach in #9383
• [CombToArith] Don't reject unknown ops by @pscabot in #9394
• [Docs] Add tools page to the website and circt-verilog docs by @cowardsa in #9385
• [Transforms][MapArithToComb] Added best-effort lowering for Arith to Comb by @KavyaChopra04 in #9380
• [Arc][SplitFuncs] Ignore extern func ops by @TaoBi22 in #9393
• [ImportVerilog] Add basic event type support by @fabianschuiki in #9381
• [ArithToComb] Avoid converting float constants to HW by @fabianschuiki in #9407
• [FSMToCore] Add FSMToCore pass by @TaoBi22 in #9354
• [ImportVerilog] Replace FormatTimeOp with FormatIntOp by @fabianschuiki in #9406
• [LLHD] Add conversion ops between time and integer values by @fabianschuiki in #9405
• [Sim][MooreToCore] Added width, alignment and padding support for moore.fmt.int by @KavyaChopra04 in #9390
• [Python] Build and upload Python 3.14 wheel. by @richardxia in #9399
• [HWToLLVM] Ignore operations of other dialects by @fzi-hielscher in #9412
• [circt-test] Add options to pick only formal/simulation tests by @fabianschuiki in #9411
• [circt-test] Add supported test kind to runner config by @fabianschuiki in #9410
• [ESI] Handle possible exception in RpcServer::SendToServer by @mortbopet in #9409
• [MooreToCore][Sim] Added support for moore.fmt.real by @KavyaChopra04 in #9397
• Fix isSeqMem() check to allow externalization of memories with read-/write-latency >= 1 by @trmckay in #9419
• [LLHD] Processes with timed waits are not combinational by @fabianschuiki in #9422
• [circt-test] Install test runners alongside circt-test by @fabianschuiki in #9413
• [circt-test] Add Verilator test runner by @fabianschuiki in #9414
• [HW] Add pass to convert bitcast operations by @fzi-hielscher in #9425
• [arcilator][HWToLLVM] Use HWConvertBitcasts pass in arcilator pipeline by @fzi-hielscher in #9426
• [CI] Set timeout to individual lit tests by @uenoku in #9424
• [circt-test] Reuse firtool pipeline to emit split verilog by @fabianschuiki in #9427
• [CombToLLVM] Add conversion for comb::ReverseOp to LLVM dialect by @yassinz in #9431

New Contributors

• @KavyaChopra04 made their first contribution in #9317
• @pscabot made their first contribution in #9394

Full Changelog: firtool-1.138.0...firtool-1.139.0

firtool-1.138.0

What's Changed

• Bump LLVM by @7FM in #9235
• [Comb] Canonicalize power-of-two unsigned div/mod. by @uenoku in #9177
• [Datapath] Prevent FoldAddIntoCompress from introducing datapath ops from pure comb ops by @uenoku in #9178
• [PyCDE] Add support for union types by @teqdruid in #9242
• [ESI] Window lowered type fix by @teqdruid in #9243
• [PyCDE] Add support for ESI Windows by @teqdruid in #9244
• [PyCDE] Add Window.default_of to simplify window creation by @teqdruid in #9248
• [HWToLLVM][ArcToLLVM] Spill array values early by @fzi-hielscher in #9218
• [NFC][Docs] Add slang flag to getting started notes by @dobios in #9249
• [OM] Add UnknownValue to Evaluator by @seldridge in #9247
• [domaintool] Add -assign u support by @seldridge in #9251
• [Synth] Fix dependency in CMakeLists by @pineapplehunter in #9254
• [HWToBTOR2] Ignore printf related operations by @dobios in #9250
• [FIRRTL] Added getExtModuleName to FExtModuleOp to get the appropriate module name by @MrRoy09 in #9233
• [Arc][Python] Add Arc API bindings and dialect support by @yassinz in #9255
• [ci] Change static build to use Rocky Linux 8 by @seldridge in #9259
• [MooreToCore] Fix lowering of dynamic extracts of nested arrays by @fzi-hielscher in #9257
• [Synth] Add an API to get value for Object by @uenoku in #9261
• [Tests][Arcilator] Move arcilator JIT tests to integration tests by @fzi-hielscher in #9265
• [Comb] Add AssumeTwoValued pass by @TaoBi22 in #9264
• [Docs][NFC] Drop outdated hw comparison by @TaoBi22 in #9270
• [SwitchToIf] support multi-result scf.index_switch + add regression test by @Bynaryman in #9245
• [Comb] Add Truth Table Simplification Pass by @MrRoy09 in #9271
• [CombFolds] Fix crash in folding with non-integer attribute operands by @uenoku in #9273
• [NFC][Docs] Update README.md with enhanced build instructions for CIRCT by @doofin in #9203
• [HW] Add pass to parameterize constant ports on private modules. by @uenoku in #9266
• [circt-test] Add simulation test discovery by @fabianschuiki in #9279
• [Transform] Add convert-index-to-uint transform to normalize index compares before comb mapping by @Bynaryman in #9263
• [HW] Enhance FlattenModules pass with configurable inlining heuristics by @prithayan in #9224
• [circt-reduce] Support dialect plugins by @maerhart in #9282
• [FIRRTL] Fix crash in getPort(size_t) when missing inner symbols. by @dtzSiFive in #9284
• FileCheck linting: fix directive typos in tests by @dtzSiFive in #9286
• [HW][NFC] Add BitWidthTypeInterface for extensible bit width calculations by @Copilot in #9272
• [ESI] Add getBitWidth to ESI types by @teqdruid in #9289
• [ESI][LowerTypes] Add support for lowering embedded windows by @teqdruid in #9290
• [CI] Disable flaky Verilog LSP tests on macOS by @fabianschuiki in #9293
• [ESI][Runtime] Basic Window and List support by @teqdruid in #9267
• [Python] Add Pipeline dialect to Python bindings by @yassinz in #9276
• [Python] Add LLVM IR export support to Python bindings by @yassinz in #9275
• [ExportVerilog] Add disallowDeclAssignments lowering option. by @uenoku in #9298
• [Verif] Lower simulation tests to HW modules by @fabianschuiki in #9294
• [circt-synth] Disable test if yosys-abc unavailable by @fabianschuiki in #9295
• [LTL] Add Boolean Constant Op, use in Implication Canonicalizer by @seldridge in #9280
• [Comb] Add ConcatOp custom assembly format to enable nullaries by @TaoBi22 in #9274
• [ESI][Data windows] Add bulk transfer encoding by @teqdruid in #9299
• [OM] Remove Pure from ObjectOp to preserve identity by @fabianschuiki in #9303
• [Verif] Add more AssertLike canonicalizers by @seldridge in #9281
• [HW][Comb][ESI] Create a common function for HW constant materialization and add null check by @uenoku in #9300
• [FIRRTL] Add anonymous domain create op by @seldridge in #9296
• [HW] Add HWBypassInnerSymbols pass by @uenoku in #9291
• Per-module GrandCentral files when no bind file is specified by @trmckay in #9305

New Contributors

• @pineapplehunter made their first contribution in #9254
• @MrRoy09 made their first contribution in #9233
• @Bynaryman made their first contribution in #9245
• @doofin made their first contribution in #9203
• @Copilot made their first contribution in #9272
• @trmckay made their first contribution in #9305

Full Changelog: firtool-1.137.0...firtool-1.138.0

firtool-1.137.0

What's Changed

• Bump LLVM by @uenoku in #9170
• [MooreToCore] [1/4] Implement ClassDeclOp -> LLVMStructType conversion by @Scheremo in #9150
• [ImportVerilog] Also ignore TypeParameterSymbol in ClassDecl by @Scheremo in #9167
• [DatapathToComb] Simplify AND Array Lowering by @cowardsa in #9160
• [MooreToCore] [2/4] Add support to lower ClassNewOp to llvm.malloc by @Scheremo in #9151
• [MooreToCore] [3/4] Add support for lowering moore.class.upcast by @Scheremo in #9152
• [MooreToCore] [4/4] Add support for class.property_ref by @Scheremo in #9153
• [HWToLLVM] Do not take illegal shortcut in array_get lowering. by @fzi-hielscher in #9172
• [Arcilator] Print full values rather than truncating them. by @SimonEbner in #9120
• [ArcIntegrationTests] Match only full output lines, NFC by @fzi-hielscher in #9174
• [RTG][Elaboration] Fix incorrect set equality by @maerhart in #9175
• [FIRRTL] Support domain.define in LowerDomains by @seldridge in #9108
• [ImportVerilog] Add global variable support by @fabianschuiki in #9176
• [HWToBTOR2] Support unary case of variadics by @TaoBi22 in #9169
• [Conversion] Add comprehensive CombToLLVM conversion pass with func.func-only scope by @prithayan in #9105
• [ImportVerilog] Fix LValue generation for ClassPropertySymbol by @Scheremo in #9182
• [ImportVerilog] Enforce base class elaboration by @Scheremo in #9181
• [HWToBTOR2] Support variadic concat ops by @TaoBi22 in #9184
• [ESI] Telemetry implementation exposing metrics over MMIO by @teqdruid in #9185
• [RTG] Add ConstraintOp by @maerhart in #9186
• [RTG] Add alloc side-effect to virtual_reg, memory_block_declare, and memory_alloc by @maerhart in #9187
• [RTG] Folders for label decl ops by @maerhart in #9188
• [RTG] Add SetAttr and TupleAttr by @maerhart in #9189
• [FIRRTL] XorRCat canonicalizer: return success when successful by @maerhart in #9192
• [Arc][LLHD] Notify rewriter when modified-in-place in canonicalizers by @maerhart in #9193
• [HWToBTOR2] Add support for comb.replicate by @TaoBi22 in #9196
• [FIRRTL] Add domain support to instance choice by @rwy7 in #9197
• [FIRRTL] Add domain verification to instance-like ops by @rwy7 in #9074
• Add sv.module.verbatim op and use for firrtl.extmodule with BlackBoxInlineAnno/BlackBoxPathAnno by @tmckay-sifive in #9131
• [Moore][ImportVerilog] Implement support for virtual functions by @Scheremo in #9180
• Bump LLVM by @jpienaar in #9194
• [ESI][BSP] Introduce a pipelined channel demux and use it by @teqdruid in #9202
• [ImportVerilog][Moore] Add toupper and tolower string builtins by @TaoBi22 in #9200
• [circt-bmc][circt-lec] Add missing headers by @uenoku in #9201
• [RTG] Remove fixed_reg operation by @maerhart in #9204
• [HWToSMT] Add forsmt-lib-export flag by @TaoBi22 in #9198
• [MooreToCore] Error out on conversions to unsupported types by @TaoBi22 in #9199
• Fix inout port lowering for sv.verbatim.module by @tmckay-sifive in #9209
• [Verif] Always add clock trigger to HasBeenReset process by @fabianschuiki in #9212
• [Moore][ImportVerilog] Add SystemVerilog string.getc builtin by @TaoBi22 in #9220
• Revert addition of sv.verbatim.module by @tmckay-sifive in #9223
• [RTG] Add ImplicitConstraintOpInterface by @maerhart in #9205
• [arcilator] Add ability to specify args from CLI by @jpienaar in #9225
• [Arcilator] Timing scopes for JIT by @SimonEbner in #9210
• [Arcilator] Move pipeline into separate library. by @SimonEbner in #9213
• [ESI] Update esitester by @teqdruid in #9226
• [circt-verilog] Move pipeline into ImportVerilog. by @SimonEbner in #9208
• [ESI] List support in data windows by @teqdruid in #9228
• [ESI][Python] Plumb through windows types to Python by @teqdruid in #9231
• [ESI] Improve error message on type registry aliasing by @mortbopet in #9229
• [PyCDE] Removing pycde.types.types functionality by @teqdruid in #9237
• [Python] Add support for UnionType by @teqdruid in #9236
• [Moore][ImportVerilog] Add VTableOps and CreateVTables pass by @Scheremo in #9221
• [ESI][Runtime] Fixing service uniquifaction by @teqdruid in #9239
• [ESI][Runtime] Add JSON output for esiquery telemetry by @teqdruid in #9240
• Add sv.verbatim.source and sv.verbatim.module ops for inline black box extmodules by @tmckay-sifive in #9227
• [HWLegalizeModules] transform mux of array to muxes of elements by @ollef in #9230

Full Changelog: firtool-1.136.0...firtool-1.137.0

firtool-1.136.0

What's Changed

• [LLHD] Allow multiple layers of inlined functions to be followed by the same op by @georgerennie in #9119
• [Comb] Integer Overflow Analysis by @cowardsa in #9130
• [FIRRTL] Various reduction pattern tweaks by @fabianschuiki in #9132
• [Moore] [1/4] Implement ClassHandleType, ClassDeclarationOp by @Scheremo in #9133
• [Moore] [2/4] Implement new operator by @Scheremo in #9134
• Move to OpTy::create, OpBuilder::create is deprecated. by @dtzSiFive in #9142
• [ImportVerilog] Use initializer list for Cases, fix deprecation. by @dtzSiFive in #9143
• [Moore] [3/4] Implement class member access, upcast by @Scheremo in #9135
• [MooreToCore] Create implicit zero value for real variables by @fabianschuiki in #9147
• [Comb] Fix another recursive mux canonicalizer by @TaoBi22 in #9144
• [circt-bmc] add verif.formal support by @TaoBi22 in #9145
• [FIRRTL] Remove dead annotations relating to taps and blackboxes. by @dtzSiFive in #9146
• [FIRRTL] Remove GC DataTaps, unused upstream. by @dtzSiFive in #9149
• [Moore] Make names of constant ops more uniform by @fabianschuiki in #9148
• [Moore] [4/4] Implement direct class method calls by @Scheremo in #9136
• [FIRRTL] Remove internalPaths from IR. Drop ref statements. by @dtzSiFive in #9154
• Reland "[Moore] Implement direct class method calls" by @Scheremo in #9156
• [ImportVerilog] Fix capture callback chaining by @Scheremo in #9165
• [Bug][ImportVerilog] [1/2] Add support for class method forward decls by @Scheremo in #9158
• [ImportVerilog] [2/2] Add support to materialize ctor call on new call by @Scheremo in #9159
• [ImportVerilog] Add support for specialized parametric classes by @Scheremo in #9161
• [ImportVerilog][Moore] Add len string builtin by @TaoBi22 in #9163
• [HWToSMT] Add option to assert equalities over module outputs by @TaoBi22 in #9162
• [HWToBTOR2] Add support for (most) variadic ops by @TaoBi22 in #9155
• [NFC] Change name in BTOR2 test by @TaoBi22 in #9168

New Contributors

• @georgerennie made their first contribution in #9119

Full Changelog: firtool-1.135.0...firtool-1.136.0

firtool-1.135.0

What's Changed

• [FIRRTL] Add support for domain-connect driving instance-choice ports by @rwy7 in #9116
• [ImportVerilog] Add variableAssignCallback, allow LHS capture by @Scheremo in #9109
• [ImportVerilog] [2/2] Add post-pass to rewrite recursive call sites by @Scheremo in #9111
• [ImportVerilog] Harden SVReal materialization by @Scheremo in #9113
• [FIRRTL] getPortNameStr to getPortName, getPortName to getPortNameAttr by @rwy7 in #9117
• [ImportVerilog] Fix dynamic part-select index typing and add test by @Scheremo in #9114
• [Synth][LowerVariadic] Fix a dialect dependency by @uenoku in #9118
• [ImportVerilog] Add support for string materialization by @Scheremo in #9112
• [FIRRTL] Add more port-related functionality to instance ops by @rwy7 in #9125
• [FIRRTL] Make containingModule compatible with Chisel changes by @fabianschuiki in #9126
• [ImportVerilog] Support real-to-integer conversion in format string by @Scheremo in #9123
• [Moore][ImportVerilog] Add real-valued ops + real-aware import; refactor logical handling by @Scheremo in #9122
• [ESI] Add bitvector and arbitrary-width integer classes by @mortbopet in #9129
• Bump LLVM by @uenoku in #9121
• [Synth] Refactor and expose dropNonCriticalPaths to Python bindings by @uenoku in #9141
• [Python] Add regression check for OpOperand owner having wrong type by @fabianschuiki in #9139

Full Changelog: firtool-1.134.0...firtool-1.135.0

firtool-1.134.0

What's Changed

• [circt-verilog-lsp] Move to Slang's src mngr, drop LLVM src mngr by @Scheremo in #9045
• [circt-verilog-lsp][NFC] Break out implementation classes by @Scheremo in #9051
• [circt-verilog-lsp] Avoid recursing into other buffers when indexing by @Scheremo in #9055
• [RTG] Implement getAsmResultNames for FixedRegisterOp by @maerhart in #9058
• [CombToDatapath] Lower comb::SubOp by @uenoku in #9053
• [circt-synth] Allow AIGER file to be an input file by @uenoku in #9054
• [ESI] ChannelMMIO: decrease MMIO space per client by @teqdruid in #9062
• [RTG][EmbedValidationValuesPass] Allow ID duplicates if values match by @maerhart in #9061
• [RTG] Add isa.space operation by @maerhart in #9060
• [circt-verilog-lsp] Refactor VerilogIndex, add Package indexing by @Scheremo in #9065
• [CombToSynth] Compute Kogge-Stone prefix tree lazily in unsigned comparison lowering by @uenoku in #9050
• [ESI] Various tweaks to cosim scripts by @mortbopet in #9064
• [ESI][Runtime] Search for backends via env var by @teqdruid in #9070
• [RTG] Add VirtualRegisterConfigAttr by @maerhart in #9059
• [Comb] Fix mux canonicalizers for non-signless-ints by @teqdruid in #9071
• [circt-verilog-lsp] Minimize project-scope File IO by @Scheremo in #9056
• [circt-lsp-verilog] "Debounce" onDidChange calls; update in worker by @Scheremo in #9046
• [circt-lsp-server] Only enable unit tests if feature is enabled by @rwy7 in #9072
• [python][Synth] Provide fine-grained APIs for path queries by @uenoku in #9068
• [ImportVerilog][MooreToCore] Implement CHandle import and lowering by @Scheremo in #9077
• [ImportVerilog][MooreToCore] Re-land Implement CHandle import and low… by @Scheremo in #9079
• [FIRRTL] Add LowerDomains pass by @seldridge in #8929
• [MooreToCore] Support slicing of nested arrays by @SimonEbner in #9073
• [LLHD] Remove unused passes and unused memory types and ops by @fabianschuiki in #9078
• [circt-verilog-lsp-server] Simplify MaxCapForcesFlushDuringContinuousTyping by removing bakground thread by @uenoku in #9080
• [LLHD] Add new RefType to replace hw::InOutType by @fabianschuiki in #9081
• Fix minor typos by @SimonEbner in #9084
• [circt-lsp-server] Make time source injectable by @Scheremo in #9082
• [ImportVerilog] Add delayed assignment support by @fabianschuiki in #9085
• Revert "[circt-lsp-server] Make time source injectable" by @Scheremo in #9089
• [ImportVerilog][Moore] Add real-to-int & int-to-real operators by @Scheremo in #9088
• [FIRRTL] Add fields to domains by @seldridge in #9087
• [Synth] Enhance LowerVariadic pass with timing-aware optimization by @uenoku in #9086
• [Synth] Add MaximumAndCover Pass by @uenoku in #9090
• [ImportVerilog] Generalize materialization of constant real values by @Scheremo in #9092
• Bump LLVM to 3c53adec68b3e7be3d69bc4e24168e530097fce0. by @mikeurbach in #9063
• [FIRRTL] Add DomainDefineOp by @rwy7 in #9067
• [FIRRTL] DomainFieldAttr types are PropertyTypes by @seldridge in #9094
• Bump Slang to v9.1 by @fabianschuiki in #9097
• [FIRRTL] Update port insertion/erasure API for instance/instance-choice ops by @rwy7 in #9093
• [Synth][LowerVariaidc] Fix topological ordering and a pass phase ordering by @uenoku in #9095
• [ESI] Add opt-out of reversal in array C++ ser/de by @mortbopet in #9096
• [FIRRTL] Add LowerDomains to firtool pipeline by @seldridge in #9099
• [MooreToCore] Lower moore.real_constant to arith.constant by @Scheremo in #9100
• [FIRRTL] Fix dedup looking up wrong op in inner ref target check by @fabianschuiki in #9104
• [ImportVerilog] Allow functions to capture values from parent scope by @Scheremo in #9107
• [Synth] Fix race condition and memory corruption in longest path analysis caching by @uenoku in #9098

New Contributors

• @SimonEbner made their first contribution in #9073

Full Changelog: firtool-1.133.0...firtool-1.134.0