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Add OSS CI to cross-compile and run the Cadence Xtensa backend#20208

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Add OSS CI to cross-compile and run the Cadence Xtensa backend#20208
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cadence-xtensa-oss-ci

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@aliafzal aliafzal commented Jun 10, 2026

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Summary

Adds OSS CI to cross-compile and run the Cadence (Xtensa) backend, so backend changes can be validated in CI rather than only through internal flows.

  • gflags-free ISS runner (cadence_executor_runner): the upstream executor_runner can't cross-compile to Xtensa (gflags pulls in mkdir(2), absent from Xtensa newlib). This uses argv-only parsing like the Arm/NXP backends, loads a .pte, and runs the first method on the simulator. Also registers the quantized_depthwise_conv1d ops the HiFi4 codegen references but the operators CMake omitted (broke the link).
  • xtensa-build job added to the existing Cadence Build & Test workflow (build-cadence-runner.yml), alongside the host cpu-build/cpu-test. It cross-compiles the runner for the hifi4 and vision cores and uploads it; an ISS test stage follows later (cf. cpu-build -> cpu-test). The licensed toolchain/core artifacts are fetched at runtime from an auth-gated store via a short-lived OIDC credential; role/region/store are supplied via CI variables and are not committed.

fusion_g3 is omitted from the matrix until an upstream operator/nnlib API skew is resolved (its runner does not link yet).

Test plan

Validated locally end to end: setup + cross-compile produce an Xtensa ELF runner for vision; the HiFi4 op sweep passes 15/15 on the simulator and a trivial model returns the expected output.

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🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/20208

Note: Links to docs will display an error until the docs builds have been completed.

❌ 2 New Failures, 1 Pending, 1 Unrelated Failure, 2 Unclassified Failures

As of commit 4916383 with merge base 5526971 (image):

NEW FAILURES - The following jobs have failed:

UNCLASSIFIED FAILURES - DrCI could not classify the following jobs because the workflow did not run on the merge base. The failures may be pre-existing on trunk or introduced by this PR:

BROKEN TRUNK - The following job failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

This comment was automatically generated by Dr. CI and updates every 15 minutes.

@meta-cla meta-cla Bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Jun 10, 2026
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Comment thread .github/workflows/build-cadence-runner.yml Fixed
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from 8e042d8 to 30d7f1a Compare June 10, 2026 22:43
Comment thread .github/workflows/build-cadence-runner.yml Fixed
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch 2 times, most recently from e8c55b5 to 7ddf69e Compare June 10, 2026 23:20
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from 7ddf69e to 80826eb Compare June 10, 2026 23:22
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from 80826eb to 99f50c8 Compare June 10, 2026 23:26
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from 99f50c8 to 8fc2df7 Compare June 10, 2026 23:29
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from 8fc2df7 to aec6ba7 Compare June 10, 2026 23:54
@aliafzal aliafzal force-pushed the cadence-xtensa-oss-ci branch from aec6ba7 to e1f804b Compare June 11, 2026 00:09
The upstream executor_runner cannot cross-compile to Xtensa because gflags pulls
in mkdir(2), absent from Xtensa newlib. Add cadence_executor_runner, a
gflags-free ExecuTorch runner for the Cadence Xtensa cores targeting the
Instruction Set Simulator (xt-run): it uses plain argv parsing like the Arm and
NXP backends, loads a .pte via xt-run semi-hosting, runs the first method with
all-ones inputs, and prints outputs. EXECUTORCH_BUILD_CADENCE_RUNNER builds it,
linking cadence_ops_lib transitively (no --whole-archive, which would double-run
static kernel registration); -lidma is linked only for Vision/Fusion-G3 cores,
whose ops reference iDMA and whose LSPs ship libidma, while HiFi4 does not. Also
register op_quantized_depthwise_conv1d_{ncl,nlc}.cpp in the HiFi4 operators
CMakeLists, which codegen references (omitting the sources broke the
cross-compile link).

Add an xtensa-build job to the Cadence Build & Test workflow
(build-cadence-runner.yml), alongside the existing host cpu-build/cpu-test, to
cross-compile the backend for the Xtensa cores. It is a build stage producing a
runner artifact; the ISS test stage follows separately (cf. cpu-build ->
cpu-test). The Xtensa toolchain and core configs are licensed and fetched at
runtime from an auth-gated object store via a short-lived OIDC credential; the
role, region, and store are supplied through CI variables and are not committed.
setup-xtensa-tools.sh downloads and installs the toolchain/core for a backend,
rewrites the vendor params to local paths, and exports the Xtensa env;
build-cadence-xtensa.sh cross-compiles cadence_executor_runner. The job builds a
[hifi4, vision] matrix and uploads the runner.

fusion_g3 is omitted from the matrix until the upstream fusion_g3 <-> nnlib API
skew is fixed (its runner does not link).
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