Cortex-M: add opt-in explicit layout lowering

[rascani]

Thread an experimental explicit-layout mode through the shared Edge compile
configuration, AOT compiler, quantizer, tester, and pass manager while retaining
legacy dim-order export as the default.

Explicit mode disables dim-order operators, converts Conv1d through the common
transform, runs the common channels-last pipeline, lowers anchors to the fixed
_nhwc schemas, and lowers surviving boundaries to cortex_m transpose. Output
dequantization remains a layout barrier, and unequal-shape add or multiply stays
outside the region until separately admitted.

Remove identity clones once qparams are folded, so explicit mode does not need a
second clone operator in the selective build. The pass has to run after folding:
removing clones first changes the quantize topology the fold matches and splits
the layout region in two.

Package the host test harness and assert expected Cortex-M targets before
planned-memory comparisons.

Local Corstone-300 run of the full Cortex-M suite, the common-transform suites,
and lintrunner. Not run on Cortex-M33.

Authored with Codex.

[rascani]

Stack from ghstack (oldest at bottom):

• Cortex-M: keep NHWC channel broadcasts quantized #21968
• -> Cortex-M: add opt-in explicit layout lowering #21967
• Cortex-M: make quantized add and multiply layout-agnostic #21966
• Cortex-M: add a contiguous-layout pad operator #22028
• Cortex-M: add explicit-NHWC runtime operators #21965
• Cortex-M: share layout-aware CMSIS-NN kernels #21964
• Channels last: add the common layout pipeline #21963
• Channels last: optimize structural layout regions #21962
• Channels last: teach the data-movement passes both permute dialects #22003

[pytorch-bot]

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