Cortex-M: add explicit-NHWC runtime operators - #21965
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21965
Note: Links to docs will display an error until the docs builds have been completed. ❌ 2 New Failures, 3 Cancelled Jobs, 6 Unrelated FailuresAs of commit 944adfd with merge base 8b93850 ( NEW FAILURES - The following jobs have failed:
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BROKEN TRUNK - The following jobs failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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Add fixed-layout NHWC-logical schemas for quantized convolution, depthwise
convolution, transpose convolution, average pooling, and max pooling.
Each wrapper lives beside its legacy entry point and selects NHWCLogical in the
shared implementation, so operator identity carries the serialized layout
contract without a general-purpose runtime parameter. Register the schemas,
Python reference implementations, scratch sizing, selective runner entries, and
host and FVP coverage.
Padding needs no second entry point: reading its sizes through the tensor's dim
order gives physical order under either contract, so the existing operator
serves both. Harden it by validating rank and four-element padding before
indexing, and decide its output memory format from an exact dim-order test
rather than a shape heuristic that treats any unit dimension as channels-last.
Local Corstone-300 run of the full Cortex-M suite (670 passed, 4 skipped, 45
xfailed, 4 xpassed), including a grouped convolution whose packed weight has a
different channel count from its input, and lintrunner. Not run on Cortex-M33.
Authored with Codex.